Hierarchical Data Storage System Parallel Processing
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Solution Overview
Problem
Current data storage systems in multiple memory devices face inefficiencies in managing complex operations across multiple memory pages and addresses, leading to high latency and limited scalability.
Innovation Solution
A hierarchical data storage system with a main controller and multiple processors that convert host commands into recipes for sequential execution across non-volatile memory devices, enabling parallel processing and efficient management of memory operations, including page reads, writes, and erasures, while optimizing execution order and prioritization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single controller manages multiple memory devices, then device complexity is reduced, but processing speed and throughput are limited
Solution Approach 1:
The storage system divides the single controller into multiple independent processors (first processor, second processor, etc.), each capable of independently managing memory operations. This segmentation allows parallel processing of multiple commands simultaneously, increasing throughput while maintaining manageable complexity through modular design
Solution Approach 2:
The system transitions from a single-threaded sequential processing model to a multi-threaded parallel processing model by introducing multiple processors that can execute commands concurrently. This dimensional change in processing architecture enables simultaneous handling of multiple memory operations across different memory devices
2Productivity
If multiple processors are introduced to increase throughput, then processing speed improves, but device complexity increases
Solution Approach 1:
Each processor in the multi-processor system is designed with identical multi-functional capabilities to execute various types of memory commands (read, write, erase, validate). This universality allows processors to be dynamically allocated to different tasks based on system needs rather than requiring specialized dedicated controllers for each function
Solution Approach 2:
The system dynamically adjusts operational parameters such as command allocation, memory address mapping, and processor workload distribution based on real-time system state. This parameter optimization enables efficient utilization of multiple processors without requiring proportional increases in system complexity
3Device complexity
If commands are processed sequentially, then device complexity is low, but latency increases
Solution Approach 1:
The system implements command queuing and pre-processing mechanisms where incoming commands are buffered, validated, and prepared for execution before actual memory operations begin. This preliminary action allows the system to minimize idle time and reduce latency by having commands ready for immediate processing when memory devices become available
Solution Approach 2:
Multiple processors enable continuous overlapping execution of memory operations, where while one processor is waiting for a memory operation to complete, another processor can simultaneously execute different operations on different memory devices. This continuity eliminates idle waiting time and reduces overall command execution latency
4Device complexity
If memory operations are managed centrally, then coordination is simplified, but scalability is limited
Solution Approach 1:
The centralized memory management functionality is segmented and distributed across multiple independent processors, each capable of autonomously managing its assigned memory operations. This segmentation enables the system to scale by simply adding more processors and memory devices without requiring redesign of the coordination architecture
Solution Approach 2:
The system introduces an address translation and command routing intermediary layer that mediates between host commands and the distributed processors. This intermediary enables scalable architecture by translating logical addresses to physical locations and routing commands to appropriate processors without requiring complex direct coordination between all system components
Data Source
AI summary
A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.