Hierarchical Data Transformation Verification by Formal Abstraction

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Solution Overview

Problem

Formal verification tools face difficulties in verifying hardware designs for data transformation components, particularly those involving complex sequences of data transformations, due to the unmanageable number of simulation test signals and the inability to solve mathematical problems within a reasonable time.

Innovation Solution

A hierarchical verification method is employed, where the hardware design for a main data transformation component is represented as a set of leaf and parent data transformation components. Leaf components are verified individually, and parent components are abstracted with corresponding components that produce specific output transactions based on causal deterministic relationships, using formal verification tools to simplify the verification process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If simulation-based verification is used to verify hardware design for data transformation components, then verification completeness can be achieved, but verification time becomes unmanageably long (millions of years for complex components)

Engineering Contradiction:

Improveverification completenessVSAvoidverification time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The hardware design is segmented into multiple hierarchical levels (leaf data transformation components and parent data transformation components). Formal verification is applied at each level separately, breaking down the overwhelming verification task into manageable segments that can be verified independently and efficiently.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Leaf data transformation components are verified in advance before assembling parent components. This preliminary verification ensures that basic building blocks are correct, reducing the complexity of verifying higher-level components and avoiding the need to verify all possible transactions from scratch.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If formal verification is used to verify hardware design, then verification time is reduced significantly, but the ability to verify complex sequences of data transformations is limited due to unmanageable mathematical problem complexity

Engineering Contradiction:

Improveverification timeVSAvoidmathematical problem complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

Complex data transformation sequences are segmented into smaller, independent data transformation stages. Each stage is verified separately using formal verification methods, reducing the mathematical problem complexity at each verification step while maintaining overall verification effectiveness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The verification focuses on verifying representative transactions and critical paths rather than exhaustively verifying every possible transaction. This partial action approach achieves sufficient verification coverage without overwhelming mathematical complexity.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If the number of simulation test signals is increased to achieve thorough verification, then verification completeness improves, but the unmanageable number of test vectors makes the process impractical

Engineering Contradiction:

Improveverification completenessVSAvoidnumber of test vectors

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The verification process is segmented by hierarchical level, with test vectors generated and applied at each level independently. This reduces the total number of test vectors needed compared to exhaustive testing at the top level, as tests are performed on smaller, more manageable components.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Verified leaf components serve as universal building blocks that can be reused in multiple parent component configurations. Once a leaf component is verified, it can be instantiated multiple times without requiring additional verification of its internal logic, reducing redundant testing.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12373621B2Verification of hardware design for data transformation component

Publication Date: 2025.07.29 IMAGINATION TECH LTD

AI summary

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.