Hierarchical DCA Training for Memory Clock Duty Cycle Tuning
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Solution Overview
Problem
Existing DCA training methods for semiconductor memory devices face challenges such as excessive time delay in setting optimal duty cycles and potential failure due to Command Even Gap violations, leading to deteriorated signal integrity at high data transfer speeds.
Innovation Solution
A hierarchical DCA training method that involves three-step DCA training processes with progressively smaller offset sizes, combined with a tie-break algorithm to select the optimal DCA code, ensuring precise adjustment of internal clock signals QCLK, IBCLK, and QBCLK to maximize the eye window size of data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DCA training method is used to adjust duty cycle of internal clock signals, then signal integrity can be improved, but training time becomes excessively long
Solution Approach 1:
The patent divides the DCA training process into multiple stages (coarse training and fine training), where each stage uses different offset sizes. The coarse training stage uses larger offsets to quickly establish a baseline, while the fine training stage uses smaller offsets to precisely optimize the duty cycle. This segmentation resolves the contradiction by reducing overall training time while maintaining signal integrity through progressive refinement.
Solution Approach 2:
The patent performs preliminary coarse training before fine training, establishing an initial duty cycle configuration that is close to optimal. This preliminary action reduces the search space for subsequent fine training, thereby significantly reducing the total training time while ensuring final signal integrity through the refinement stage.
2Reliability
If DCA code is applied to improve read margin, then data signal quality can be enhanced, but Command Even Gap violation may occur causing training failure
Solution Approach 1:
The patent dynamically adjusts the DCA code application strategy based on command sequence analysis. Before applying DCA codes, the system checks whether the command sequence satisfies the even condition. If the condition is not met, the system adjusts the training approach or skips DCA code application for that particular sequence, thereby preventing Command Even Gap violations while still achieving good read margin when conditions permit.
Solution Approach 2:
The patent incorporates feedback mechanisms where the training system monitors command sequence characteristics and adjusts DCA code application accordingly. When Command Even Gap violations are detected or predicted, the system modifies its training approach in real-time, ensuring training success while maintaining optimal read margin through adaptive DCA code selection.
Data Source
AI summary
A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.