Hierarchical Decoder Control for BER-Latency Tradeoffs

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Solution Overview

Problem

Existing decoding algorithms face a trade-off between computational complexity and bit error rate (BER) performance, with simple algorithms insufficient in poor channel environments and complex algorithms increasing processing latency and power consumption.

Innovation Solution

A decoding apparatus with multiple decoder stages and a controller that dynamically selects decoding algorithms based on the bit error rate (BER) of a received signal, using a hierarchical approach to switch between algorithms of varying computational complexity to ensure successful decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a complex decoding algorithm is used, then BER performance is improved, but computational complexity and power consumption increase

Engineering Contradiction:
ImproveBER performanceVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The decoding process is divided into multiple stages, each applying a different decoding algorithm with varying complexity. The controller segments the decoding task by selecting appropriate algorithms based on channel conditions, thereby reducing overall computational complexity while maintaining BER performance through hierarchical processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoding apparatus dynamically selects and switches between different decoding algorithms based on real-time channel conditions and BER requirements. This dynamic adaptation allows the system to use simpler algorithms when possible, reducing computational complexity and power consumption, while transitioning to more complex algorithms only when necessary for poor channel conditions.

Inventive Principle:
Principle #15Dynamics

2Reliability

If a complex decoding algorithm is used, then BER performance is improved, but processing latency increases

Engineering Contradiction:
ImproveBER performanceVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The decoding process is segmented into multiple stages with increasing algorithm complexity. By processing signals through simpler algorithms first in earlier stages, the system reduces overall processing time for good channel conditions, while reserving more complex algorithms for later stages only when simpler methods fail, thus optimizing latency-performance tradeoff.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller performs preliminary assessment of channel conditions and BER requirements before selecting the decoding algorithm. This preliminary action allows the system to choose the most appropriate algorithm in advance, avoiding unnecessary execution of complex algorithms when simpler ones suffice, thereby reducing processing latency while maintaining BER performance.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a complex decoding algorithm is used, then BER performance is improved, but power consumption increases

Engineering Contradiction:
ImproveBER performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The decoding functionality is segmented across multiple stages with progressively more complex algorithms. This segmentation enables the system to consume less power by utilizing simpler algorithms in earlier stages for good channel conditions, and only activating more power-intensive complex algorithms in later stages when necessary for poor channel conditions, thereby optimizing the power-BER tradeoff.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoding apparatus dynamically adjusts algorithm selection based on channel conditions to optimize power consumption. By transitioning between different decoding algorithms with varying power requirements, the system minimizes power consumption for good channel conditions while ensuring adequate BER performance is maintained when channel conditions deteriorate.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8347194B2Hierarchical decoding apparatus
Publication Date: 2013.01.01 SAMSUNG ELECTRONICS CO LTD
  • US8347194B2 patent drawing
  • US8347194B2 patent drawing
  • US8347194B2 patent drawing

AI summary

A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.