Hierarchical Digital Circuit Simulation Using State Nodes and Lookup Tables
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Solution Overview
Problem
Conventional device level digital integrated circuit simulators require flattening hierarchical circuits to the transistor level, leading to inefficient simulations due to repeated simulations of identical circuit modules, which is time-consuming and memory-intensive.
Innovation Solution
A hierarchical digital simulator that utilizes a native module hierarchy, employing look-up tables to store and reuse simulation results for identical circuit modules, and defines 'state nodes' to efficiently manage sequential circuits by storing only necessary state information, thereby reducing simulation time and memory overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional simulators flatten hierarchical circuits to transistor level, then simulation compatibility is achieved, but simulation time and memory usage increase significantly
Solution Approach 1:
The patent segments the circuit simulation into hierarchical levels by maintaining the native module hierarchy structure. Instead of flattening the entire circuit to transistor level, the simulator processes circuits at their modular hierarchy levels, simulating modules as complete units rather than individual transistors. This segmentation reduces the simulation scope and avoids redundant processing of identical modules.
Solution Approach 2:
The patent employs look-up tables to store and reuse simulation results for identical circuit modules. When a module instance is encountered that has been simulated before under the same input conditions, the simulator retrieves the pre-computed results from the look-up table instead of re-simulating the module. This copying of results significantly reduces simulation time and memory usage.
2Reliability
If conventional simulators flatten hierarchical circuits to transistor level, then simulation compatibility is achieved, but memory consumption increases
Solution Approach 1:
The patent segments the circuit representation to maintain hierarchical module structures rather than flattening to transistor level. This segmentation allows the simulator to manage memory more efficiently by storing information at higher abstraction levels (module level) rather than requiring detailed transistor-level data for all components, thereby reducing overall memory consumption.
Solution Approach 2:
The patent uses look-up tables to copy and reuse simulation results for identical modules across different instances. Instead of storing complete transistor-level simulation data for every module occurrence, the system stores results once and reuses them, significantly reducing memory requirements while maintaining simulation accuracy.
3Measurement precision
If identical circuit modules are simulated separately for each occurrence, then simulation accuracy is maintained, but simulation efficiency decreases
Solution Approach 1:
The patent implements look-up tables that store simulation results for identical modules. When a module instance matches a previously simulated module under the same input conditions, the system copies the pre-computed results to the current instance, maintaining simulation accuracy while eliminating redundant computation. This copying approach preserves correctness without sacrificing efficiency.
Solution Approach 2:
The patent changes the simulation approach from processing each module instance independently to processing modules based on their identity and input parameters. By grouping identical modules and using their input conditions as keys for result retrieval, the system maintains accuracy for each instance while improving overall efficiency through parameter-based result reuse.
Data Source
AI summary
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.