Hierarchical ECC Decoding for NAND Flash Error Correction
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Solution Overview
Problem
NAND flash memory devices face challenges in error correction due to non-additive white Gaussian noise and increased complexity from vertical stacking, which decreases signal-to-noise ratio and demands stronger error-correction mechanisms, while existing decoding methods are computationally intensive and may reduce SSD performance.
Innovation Solution
A hierarchical error code correction system that uses multiple decoder hierarchies with increasing complexity, where each hierarchy shares more NAND channels and employs longer codes and more complex decoding algorithms, allowing for efficient error correction with acceptable hardware complexity and maintaining SSD performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polar decoding scheme is used for error correction, then error correction capability is improved, but computational complexity increases significantly
Solution Approach 1:
The patent segments the error correction process into two distinct hierarchies: a first decoding hierarchy using computationally intensive polar decoding algorithms for high reliability requirements, and a second decoding hierarchy using less complex LDPC decoding algorithms for routine error correction. This segmentation allows the system to achieve strong error correction capability while avoiding the computational complexity of polar decoding for all cases.
Solution Approach 2:
The patent implements a dynamic decoding hierarchy that adapts the decoding process based on error conditions. The system first attempts decoding with the simpler LDPC code, and only when errors persist does it escalate to the more complex polar decoding. This dynamic approach optimizes the balance between computational complexity and error correction capability based on actual error conditions.
2Quantity of substance
If VNAND devices increase number of layers and bits per-cells modulation, then storage density is improved, but signal to noise ratio decreases
Solution Approach 1:
The patent employs a composite error correction approach by combining two different coding schemes (polar codes and LDPC codes) into a hierarchical structure. This composite approach leverages the strengths of both codes: polar codes provide superior error correction for high-density VNAND where SNR is poor, while LDPC codes handle routine errors efficiently, thereby maintaining reliable operation despite the degraded SNR from increased storage density.
Solution Approach 2:
The patent applies prior cushioning by pre-establishing a two-layer error correction hierarchy before data is stored in the high-density VNAND device. The outer polar code layer provides a strong error correction safety net specifically designed to handle the elevated error rates from reduced SNR in high-density storage, cushioning the system against the harmful effects of increased storage density.
3Reliability
If hierarchical decoding architecture is implemented, then error correction performance is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the hierarchical decoding architecture into two distinct decoding layers with different complexity levels. The first layer uses LDPC decoding with simpler hardware requirements for common error patterns, while the second layer uses polar decoding with more complex hardware only when needed. This segmentation reduces overall hardware complexity compared to using a single high-performance decoder for all cases.
Solution Approach 2:
The patent employs a strategy where the simpler LDPC decoder is used as the primary, low-cost first line of defense for most decoding operations. The more expensive and complex polar decoder is reserved as a fallback option only when the LDPC decoder fails to correct errors. This approach minimizes hardware complexity by avoiding the need to always deploy the most powerful decoder.
Data Source
AI summary
Embodiments of the present disclosure provide a controller hierarchical decoding architecture. For instance, multiple decoder hierarchies are implemented along with use of hierarchies of codes with locality (e.g., larger code length of a hierarchy is composed of local codes from a lower hierarchy). The hierarchical Error Correction Code (ECC) decoding includes multiple hierarchies such as a first hierarchy, a second hierarchy, and additional hierarchies as needed. A first hierarchy includes low-complexity ECC engines, each connected to a NAND channel for computing local codes of low code lengths. A second hierarchy includes higher complexity ECC engines that shares several NAND channels for correcting corrupt data using relatively larger code length (e.g., and the higher complexity ECC engines of the second hierarchy performs decoding operations using more complex decoding algorithms). The larger code length is composed of local codes from a previous hierarchy.