Hierarchical Encoding with Dynamic Delay for Phase Alignment

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Solution Overview

Problem

Hierarchical encoding systems face challenges in accurately correcting phase differences over time, leading to increased bit rates due to the use of fixed delay amounts, which is inadequate for dynamic phase changes in signals processed by CELP and other encoding schemes.

Innovation Solution

A hierarchical encoding apparatus that dynamically calculates a delay amount for each frame based on the phase difference between the input signal and the first layer decoded signal, using a correlation analysis to determine the optimal delay and reduce bit rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed delay amount is used to correct phase difference, then the device complexity is reduced, but the manufacturing precision of phase alignment deteriorates over time

Engineering Contradiction:
Improvedelay section complexityVSAvoidphase alignment precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The delay amount is changed from a fixed value to a dynamically variable value that adapts to changing signal conditions. The calculating section computes the delay amount in real-time based on correlation analysis between input and decoded signals, allowing the delay section to maintain optimal phase alignment despite variations in encoding methods and signal characteristics.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

A feedback mechanism is introduced where the calculating section continuously monitors the correlation between the input signal and the decoded signal, and adjusts the delay amount accordingly. This closed-loop control ensures that the delay correction remains accurate even when phase characteristics change over time due to different encoding schemes or signal conditions.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If a fixed delay amount is used, then the ease of operation is improved, but the loss of information increases due to inadequate phase correction

Engineering Contradiction:
Improvedelay section operationVSAvoidsignal information loss
Core Design Contradiction:
Ease of operationVSLoss of information

Solution Approach 1:

The system performs self-adjustment by automatically calculating the optimal delay amount based on the actual signal characteristics. The calculating section uses correlation analysis to determine the appropriate delay without external intervention, ensuring that the delay correction adapts to changing conditions while maintaining ease of operation.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If dynamic delay calculation is implemented, then the manufacturing precision of phase alignment is improved, but the device complexity increases

Engineering Contradiction:
Improvephase alignment precisionVSAvoidencoding apparatus complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The delay correction function is segmented into two independent sections: a calculating section that computes the optimal delay amount using correlation analysis, and a delay section that applies the calculated delay. This segmentation allows the complex calculation task to be separated from the simple delay application, making the overall system more manageable and maintainable.

Inventive Principle:
Principle #1Segmentation

4Loss of information

If dynamic delay calculation is implemented, then the loss of information is reduced through accurate phase correction, but the productivity decreases due to additional calculation processing

Engineering Contradiction:
Improvesignal information lossVSAvoidencoding processing speed
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The correlation analysis is performed only on the necessary portions of the signal to determine the delay amount, rather than processing the entire signal. This partial action approach computes only the essential parameters needed for delay calculation, reducing the overall computational burden while still achieving accurate phase alignment.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7949518B2Hierarchy encoding apparatus and hierarchy encoding method
Publication Date: 2011.05.24 III HOLDINGS 12 LLC
  • US7949518B2 patent drawing
  • US7949518B2 patent drawing
  • US7949518B2 patent drawing

AI summary

A hierarchy encoding apparatus capable of calculating appropriate delay amounts and also capable of suppressing increase in the bit rate. In this apparatus, a first layer encoding part (101) encodes the input signal of the n-th frame to produce a first layer encoded code. A first layer decoding part (102) generates a first layer decoded signal from the first layer encoded code and applies it to a delay amount calculating part (103) and a second layer encoding part (105). The delay amount calculating part (103) uses the first layer decoded signal and input signal to calculate the delay amount to be added to the input signal, and applies the calculated delay amount to a delay part (104). The delay part (104) delays the input signal by the delay amount applied from the delay amount calculating part (103) and then applied it to a second layer encoding part (105). The second layer encoding part (105) uses the first layer decoded signal and the input signal from the delay part (104) for encoding.