Hierarchical Adaptive Equalizer for Faster Convergence

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing adaptive equalizers face challenges with low convergent rates and high calculation complexity, particularly in dynamic communication environments, where they struggle to minimize mean square error and maintain performance as the number of taps increases.

Innovation Solution

A hierarchical adaptive equalizer structure is introduced, dividing N delay elements into adaptive algorithms structured as a hierarchical tree with multiple levels, allowing each level to process input signals and update weightings individually, thereby enhancing convergent rate and reducing algorithmic complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional adaptive equalizer algorithms (LMS, RLS) are used, then the equalizer can process signals and reduce interference, but the convergent rate is low and calculation complexity is high

Engineering Contradiction:
Improveconvergent rateVSAvoidalgorithmic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the traditional single adaptive equalizer into multiple parallel adaptive equalizers, each processing a subset of input signals. This segmentation allows each sub-equalizer to converge faster while maintaining overall system performance, resolving the contradiction between convergent rate and computational complexity by distributing the processing load across multiple simpler units.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the number of taps in the equalizer is increased to improve performance, then the equalizer can handle more complex channel conditions, but the calculation complexity increases and convergent rate decreases

Engineering Contradiction:
Improveperformance in dynamic environmentsVSAvoidnumber of taps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of using a single equalizer with many taps, the patent segments the processing into multiple equalizers with fewer taps each. This maintains the ability to handle complex channel conditions while reducing the computational burden and improving convergent rate on each individual processor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimension approach (one equalizer with many taps) to a multi-dimensional approach (multiple equalizers with fewer taps each). This dimensional change allows the system to achieve the same or better performance by distributing complexity across multiple processing units rather than concentrating it in one unit.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If traditional equalizer structures are used, then the implementation is straightforward, but the equalizer performance degrades in worsening communication environments

Engineering Contradiction:
Improveperformance in worsening environmentsVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs multiple parallel adaptive equalizers that can independently adapt to changing channel conditions. This segmented architecture provides better performance in worsening environments by distributing the adaptation task across multiple units, each capable of tracking channel variations more effectively than a single traditional equalizer.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7421019B2Hierarchical adaptive equalizer and design method thereof
Publication Date: 2008.09.02 NAT CHUNG SHAN INST SCI & TECH
  • US7421019B2 patent drawing
  • US7421019B2 patent drawing
  • US7421019B2 patent drawing

AI summary

A hierarchical adaptive equalizer and a design method thereof are disclosed. The design method divides N delay elements into a plurality of adaptive algorithms, each of the adaptive algorithms having β delay elements. The design method logically structures a hierarchical tree with the adaptive algorithms. The hierarchical tree comprises α levels. A top first level of the hierarchical tree comprises βα−1 adaptive algorithms. A top second level of the hierarchical tree comprises βα−2 adaptive algorithms. A bottom level of the hierarchical tree comprises an adaptive algorithm.