Hierarchical Equivalence Checking with Black-Boxed ECO Blocks
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Solution Overview
Problem
Performing top-level equivalence checks for circuit designs with multiple functional blocks is challenging, especially when proprietary RTLs are not shared, leading to difficulties in verifying circuit functionality post-synthesis and applying engineering change orders (ECOs), particularly in large designs that require significant processing resources.
Innovation Solution
A hierarchical equivalence checking method is employed, where pre-verified functional blocks are 'black boxed' to reduce processing load, allowing equivalence checks to be performed efficiently by comparing lower-level logic blocks first and then the top-level circuit design, using a combination of RTL and netlist comparisons with black-boxed proprietary blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complete RTLs are available for all functional blocks, then equivalence checking accuracy is improved, but processing resources and runtime increase significantly
Solution Approach 1:
The circuit design is divided into multiple functional blocks, where some blocks (with available RTL) undergo detailed equivalence checking while others (without RTL) are treated as black boxes. This segmentation allows the verification process to focus computational resources on blocks where complete information is available, maintaining accuracy where possible while improving overall processing efficiency.
Solution Approach 2:
Different verification depths are applied to different functional blocks based on local availability of RTL information. Blocks with complete RTL receive full equivalence checking (high verification depth), while blocks without RTL receive constrained-based verification (lower verification depth). This local quality approach optimizes the balance between accuracy and processing resources.
2Productivity
If proprietary RTLs are not shared for certain functional blocks, then processing resources are reduced, but equivalence checking capability deteriorates
Solution Approach 1:
When RTL is not available for a functional block, the patent uses netlists and constrained-based verification as intermediaries to perform equivalence checking. The netlist serves as an intermediate representation that, while less detailed than RTL, still enables verification through constraint-based methods, maintaining some equivalence checking capability without requiring the proprietary RTL.
Solution Approach 2:
The patent applies partial equivalence checking to blocks without RTL by using available netlist information and constraints. While this doesn't provide complete verification (excessive action would require full RTL), it performs sufficient verification (partial action) to catch obvious errors while accepting that some verification depth is reduced for blocks where complete information is unavailable.
3Reliability
If detailed equivalence checking is performed on all blocks, then verification completeness is improved, but runtime increases significantly
Solution Approach 1:
The verification process is segmented into two streams: detailed equivalence checking for blocks with available RTL and constrained-based verification for blocks without RTL. This segmentation ensures verification completeness for the portions where it's feasible while reducing runtime by using a lighter verification approach for other blocks.
Solution Approach 2:
The patent applies partial verification to blocks without RTL by using netlist-based constrained checking. This partial action approach maintains reasonable verification completeness for the overall design while significantly reducing the runtime that would be required for full equivalence checking of all blocks.
Data Source
AI summary
An apparatus, a hierarchical method of equivalence checking a circuit design and equivalency checking after engineering change orders in a circuit design are disclosed herein. In one embodiment, a method of equivalence checking includes: (1) receiving a post-engineering change order (ECO) netlist of a first one of the functional blocks, wherein the post-ECO netlist has been verified employing an equivalence checker, (2) generating a top level netlist for the circuit design including the post-ECO netlist and a block netlist for a second one of the multiple functional blocks, (3) generating a top level register transfer level (RTL) for the circuit design including a RTL for the second functional block and (4) performing an equivalency check of the top level RTL to the top level netlist, wherein a RTL for the first functional block and the post-ECO netlist are black boxed for the performing.