Hierarchical Error Correction Codes for Low-Latency Data Protection
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Solution Overview
Problem
Existing error correction methods increase data source demands and latency due to added redundancy, and struggle with efficiently correcting bit errors beyond a certain threshold, particularly in large data words where double-bit errors require additional read operations.
Innovation Solution
Implementing a hierarchical error correction system using a linear systematic base correction code and an extended linear systematic correction code, where single-bit errors are corrected directly and double-bit errors are corrected through an extension error correction code, reducing redundancy and overhead by adapting to error probability distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capability is increased to correct more bit errors, then data reliability is improved, but data latency and redundancy increase
Solution Approach 1:
The error correction capability is segmented into multiple levels: a base correction code for single-bit errors and an extended correction code for double-bit errors. The system first attempts correction with the base code, and only if that fails does it proceed to the extended code, thereby avoiding the latency of always using the more complex extended correction.
Solution Approach 2:
The system applies partial error correction action by using the minimal necessary correction capability (base code) for most cases, and only applies the full extended correction action when the base correction fails. This avoids the excessive redundancy and latency of always using the maximum correction capability.
2Reliability
If error correction capability is increased to correct more bit errors, then data reliability is improved, but the amount of redundancy increases
Solution Approach 1:
The redundancy is segmented into two layers: base redundancy for single-bit error correction and extended redundancy for double-bit error correction. The system stores both types of redundancy but only activates the extended redundancy when needed, thereby managing the total redundancy amount efficiently.
Solution Approach 2:
The base correction code is nested within the extended correction code structure. The base code handles the majority of error cases, and the extended code provides an outer layer of protection for more severe errors. This nested structure allows the system to achieve high reliability while keeping the base redundancy level manageable.
3Device complexity
If base correction code is used for all error types, then device complexity is reduced, but double-bit errors cannot be corrected
Solution Approach 1:
The correction system is segmented into a simple base correction module for single-bit errors and an extended correction module for double-bit errors. The base module maintains low complexity for common cases, while the extended module provides enhanced capability only when needed, balancing overall system complexity with reliability.
Solution Approach 2:
An intermediary control mechanism determines whether to activate the base correction or the extended correction based on the error type. This intermediary layer manages the complexity by selectively engaging the appropriate correction level, ensuring double-bit errors can be corrected without always incurring the full complexity of the extended system.
4Reliability
If hierarchical error correction is implemented with extended code, then double-bit error correction is achieved, but processing overhead increases
Solution Approach 1:
The system applies partial processing overhead by using the lightweight base correction process for the majority of single-bit error cases. The more computationally intensive extended correction process is activated only partially, when the base correction fails to correct the error. This selective approach achieves double-bit error correction capability while minimizing average processing overhead.
Data Source
AI summary
A device for protecting a data word against data corruption includes first and second determiners. The first determiner is configured to determine an error correction code cvA associated with a data word a so that cvA=aAT, with A being a generator matrix of a linear systematic base correction code, the columns of which enable performance of an x-bit error correction on replica of the data word a and the associated error correction code cvA. The second determiner is configured to determine an extended error correction code cvE so that (cvA|cvE)=aFT, with F being an extended generator matrixF=(AE)of an extended linear systematic correction code, the columns of which enable, using the extension error correction code cvE, performance of an y-bit error correction, with y>x, on a replica of the data word a and the associated error correction code cvA.