Hierarchical Error Injection for RAIM/ECC Verification
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Solution Overview
Problem
In complex RAIM/ECC designs with large error state spaces, exhaustive verification within limited machine design cycles is challenging, and existing methods are inefficient in verifying all possible error outcomes, especially for creating and testing uncorrectable errors.
Innovation Solution
A hierarchical error injection scheme is employed to selectively inject errors into marked channels and chips, using biasing tables to guide random injections and generate specific error types, thereby increasing the likelihood of hitting critical error states and corner cases within a shorter time frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive verification is performed on all error states, then verification completeness is improved, but verification time becomes excessively long
Solution Approach 1:
The patent segments the error state space into distinct categories (correctable errors, uncorrectable errors, and specific error patterns) and applies targeted injection strategies to each segment. This allows verification to focus on critical error types rather than exhaustively testing all possible bit flip combinations, thereby reducing verification time while maintaining reliability.
Solution Approach 2:
The patent applies partial action by selectively injecting errors into specific channels and chips based on predetermined patterns and probability distributions. Instead of uniformly testing all possible error states, the system focuses injection efforts on high-risk areas, achieving effective verification coverage without the time cost of exhaustive testing.
2Ease of manufacture
If random bit flipping is used to create errors, then implementation simplicity is improved, but error state coverage becomes insufficient
Solution Approach 1:
The patent introduces dynamics into the error injection process by using probability distributions and random selection mechanisms that adaptively determine which channels and chips receive errors. This dynamic approach maintains implementation simplicity while significantly improving error state coverage compared to static random bit flipping.
Solution Approach 2:
The patent changes the parameters of error injection by controlling the number of errors injected into specific channels and chips, rather than simply flipping random bits. This parameter-based control allows systematic coverage of different error states while maintaining implementation simplicity through configurable injection rules.
3Productivity
If targeted error injection is performed on specific channels and chips, then verification efficiency is improved, but system complexity increases
Solution Approach 1:
The patent segments the injection process into hierarchical levels (channel-level selection, chip-level selection, and bit-level injection). This segmentation improves verification efficiency by systematically targeting specific components while managing complexity through modular, layered control structures.
Solution Approach 2:
The patent performs preliminary actions by pre-determining error patterns, selecting target channels and chips before actual injection occurs. This preliminary planning improves verification efficiency by focusing injection efforts on high-priority areas while reducing runtime complexity through pre-computed injection strategies.
Data Source
AI summary
A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.