Hierarchical Fill for Circuit Layout Redundancy
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Solution Overview
Problem
Conventional planarization methods in integrated circuit design often result in uneven surfaces due to differences in material density, leading to defects like holes and loss of contact, as they eliminate geometric redundancy, increasing design time for downstream checks.
Innovation Solution
A computing system that identifies and retains design features in a circuit design layout to perform hierarchical fill operations, capturing and modifying the layout to maintain redundancy, thereby reducing the time required for back-end processing while enhancing front-end modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization methods are used to improve surface flatness, then manufacturing precision is improved, but geometric redundancy is eliminated, increasing design time for downstream checks
Solution Approach 1:
The layout is divided into multiple cells that are processed independently. The fill tool generates windows corresponding to different portions of the layout and processes each portion separately, allowing downstream checks to be performed on individual cells rather than the entire layout, thus reducing overall design time while maintaining manufacturing precision
Solution Approach 2:
The hierarchy is captured from the layout before fill operations are performed. This preliminary capture of the hierarchy structure allows the system to retain geometric redundancy information that can be leveraged by downstream checks, preventing the loss of time that would otherwise occur if redundancy were eliminated
2Manufacturing precision
If fill operations are performed on the entire layout at once, then manufacturing precision is improved, but device complexity increases due to loss of hierarchical structure
Solution Approach 1:
Instead of processing the entire layout as a single unit, the system segments the layout into multiple cells and processes each cell independently through fill operations. This segmentation approach maintains the hierarchical structure by preserving cell boundaries and relationships, reducing device complexity while still achieving the necessary manufacturing precision
Solution Approach 2:
The hierarchy capture creates a nested structure where cells are organized within larger layout contexts. This nesting preserves the hierarchical relationships between different levels of the design, allowing fill operations to be performed on individual cells without disrupting the overall hierarchical structure, thus managing device complexity effectively
Data Source
AI summary
This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.