Hierarchical Finite State Machines for Compressed State Transfer

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Solution Overview

Problem

Hierarchical parallel machines face challenges in reducing data processing time due to the large amount of state information passed between finite state machine engines, which can lead to delays in real-time operations, especially as the size of the state machines increases.

Innovation Solution

Implementing a hierarchical structure with cascaded finite state machine engines where each level processes and provides output based on the previous level's output, allowing for feedback and compression of state information to reduce the data transfer burden, and using a compiler to optimize state machine implementation and image loading for efficient processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the size of state machines increases to improve pattern recognition capability, then the recognition accuracy is improved, but the data processing time increases due to large amount of state information passed between engines

Engineering Contradiction:
Improvepattern recognition accuracyVSAvoiddata processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the hierarchical parallel machine into multiple levels (first level, second level, third level) with each level containing finite state machine engines that process specific portions of state information. This segmentation allows each engine to handle a manageable subset of states while collectively maintaining high pattern recognition accuracy across the entire system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts and processes only the necessary state information at each hierarchical level rather than passing all state information between all engines. The first level engines process initial state information, the second level processes intermediate states, and the third level processes final states, extracting only relevant information at each stage to reduce overall data processing time.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If more state information is passed between finite state machine engines to improve processing accuracy, then the processing accuracy is improved, but the device complexity increases

Engineering Contradiction:
Improveprocessing accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the state processing function across three hierarchical levels, with each level containing specialized finite state machine engines. This segmentation maintains processing accuracy by ensuring each level handles specific state transitions appropriately, while reducing system complexity by organizing the information flow in a structured hierarchical manner rather than requiring all engines to process all state information.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the state processing architecture, organizing finite state machine engines into multiple levels (first level, second level, third level) rather than a flat structure. This dimensional organization allows the system to maintain high processing accuracy through specialized processing at each level while managing complexity through the hierarchical framework.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9519860B2Programmable device, hierarchical parallel machines, and methods for providing state information
Publication Date: 2016.12.13 MICRON TECHNOLOGY INC
  • US9519860B2 patent drawing
  • US9519860B2 patent drawing
  • US9519860B2 patent drawing

AI summary

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.