Hierarchical Joinable Behavior Containers for FPGA Resource Allocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing reconfigurable computing systems with field programmable gate arrays (FPGAs) face inefficiencies due to fixed-size partially reconfigurable regions, leading to suboptimal use of resources and issues like thrashing, as they are not designed to accommodate diverse hardware behaviors of varying sizes and complexities simultaneously.
Innovation Solution
The implementation of hierarchically nested and joinable hardware behavior containers allows for flexible sizing and dynamic allocation of reconfigurable resources, enabling more efficient use of FPGA resources by reconfigurable logic managers based on current workload and application requirements, through abutment and hierarchical joining of containers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed-size partially reconfigurable regions are used in FPGAs, then device reliability is protected through bus macro gate structures, but resource utilization efficiency deteriorates due to inefficient use of reconfigurable regions
Solution Approach 1:
The patent divides the FPGA device into multiple hierarchical levels of reconfigurable regions. The top level contains multiple first reconfigurable regions, each containing multiple second reconfigurable regions, and so on through multiple hierarchy levels. This segmentation allows the system to select appropriate region sizes for different hardware behaviors, improving resource utilization while maintaining device reliability through the hierarchical structure.
Solution Approach 2:
The patent enables dynamic selection of reconfigurable region sizes by allowing the system to choose from multiple hierarchical levels. Instead of fixed-size regions, the system can dynamically allocate regions of varying sizes based on the specific needs of hardware behaviors, thereby improving resource utilization efficiency while maintaining the protective bus macro gate structures.
2Reliability
If pre-determined fixed boundaries are set for partially reconfigurable regions, then device protection rules are satisfied, but adaptability deteriorates due to inability to accommodate varying hardware behavior sizes
Solution Approach 1:
The hierarchical segmentation creates multiple layers of reconfigurable regions with different sizes. This allows the system to accommodate hardware behaviors of varying sizes by selecting appropriate regions from different hierarchy levels, thereby improving adaptability while maintaining the protective boundaries through the hierarchical structure.
Solution Approach 2:
The hierarchical structure serves multiple functions: it provides device protection through bus macro gate structures, enables dynamic region size selection, and accommodates various hardware behavior sizes. This multi-functionality resolves the contradiction between maintaining protection rules and achieving adaptability.
3Stability of the object's composition
If multiple fixed-size reconfigurable regions are allocated, then device stability is maintained, but efficiency deteriorates due to thrashing when hardware behaviors vary in size
Solution Approach 1:
The patent introduces dynamic region size selection through hierarchical levels. The system can dynamically choose the appropriate size of reconfigurable regions based on the hardware behavior being loaded, reducing thrashing caused by fixed-size allocations. The hierarchical structure maintains configuration stability by providing a systematic framework for dynamic allocation.
Solution Approach 2:
The system changes the parameter of reconfigurable region size by selecting from multiple hierarchical levels. This parameter change allows the system to optimize region size for each hardware behavior, improving reconfiguration efficiency while maintaining configuration stability through the hierarchical framework.
Data Source
AI summary
A method and system for the flexible sizing of behavior containers on a reconfigurable computing resource through the use of hierarchically nested as well as joinable and separable containers is provided.