Hierarchical Partial Reconfiguration for Nested FPGA Compute Regions
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Solution Overview
Problem
The fixed boundaries and size of partial reconfiguration regions in programmable integrated circuits restrict rapid reconfiguration and fine-grained parallelism, particularly in applications like data centers, where dynamic changes in kernel operations are required.
Innovation Solution
Implementing a hierarchical partial reconfiguration method that allows for the creation of nested partial reconfiguration regions within a programmable integrated circuit, enabling flexible customization of compute regions and reducing the number of partial bitstreams needed, while maintaining uninterrupted operation of static and other reconfiguration regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fixed boundaries and size of partial reconfiguration regions are used, then reconfiguration region stability is maintained, but reconfiguration speed and fine-grained parallelism are restricted
Solution Approach 1:
The patent divides the partial reconfiguration region into multiple sub-regions with independent boundaries. Each sub-region can be reconfigured independently, enabling fine-grained parallelism and faster reconfiguration by allowing different parts of the device to be reconfigured simultaneously rather than as a single fixed block.
Solution Approach 2:
The patent implements nested partial reconfiguration regions where sub-regions are contained within larger reconfiguration regions. This hierarchical structure allows multiple levels of reconfiguration, enabling both fine-grained control at the sub-region level and coarse-grained management at the parent region level, thereby increasing reconfiguration speed without excessive complexity.
2Adaptability or versatility
If multiple partial reconfiguration regions are created, then fine-grained parallelism is enabled, but the number of partial bitstreams increases
Solution Approach 1:
The patent creates a template-based partial reconfiguration region that can be instantiated multiple times with different configurations. A single template definition can generate multiple reconfiguration regions by parameter substitution, reducing the number of unique bitstreams needed while maintaining high adaptability and fine-grained parallelism across multiple regions.
Solution Approach 2:
The patent uses template copying and instantiation to generate multiple partial reconfiguration regions from a single master template. This allows the same reconfiguration logic to be reused across multiple regions, significantly reducing the total number of bitstreams required compared to defining each region independently, while still enabling flexible and adaptable reconfiguration.
3Quantity of substance
If hierarchical reconfiguration is implemented, then bitstream storage requirements are reduced, but implementation complexity increases
Solution Approach 1:
The patent implements a hierarchical structure where parent reconfiguration regions contain child sub-regions, and templates can be nested within other templates. This nesting allows bitstream compression through inheritance, where child regions inherit common configuration elements from parent templates, significantly reducing total bitstream storage requirements while the hierarchical organization manages the implementation complexity through structured modularity.
Solution Approach 2:
The patent merges common configuration elements into parent templates that are shared by multiple child regions. By combining repeated patterns and common logic into higher-level templates, the overall bitstream size is reduced through elimination of redundancy, while the hierarchical structure provides a systematic way to manage the complexity of the combined configuration.
Data Source
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AI summary
Hierarchical partial reconfiguration for integrated circuits includes converting (415), using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading (420), using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including (435), using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented (440) with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.