Hierarchical FSM State Output Compression for Real-Time Processing
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Solution Overview
Problem
The existing technologies face challenges in efficiently processing data with hierarchical parallel machines due to the asymmetry between input and output data sizes, which can lead to significant delays, especially in real-time applications, as the state vector passed between finite state machine engines is large and complex, requiring numerous cycles to transfer effectively.
Innovation Solution
The implementation of a hierarchical structure with cascaded finite state machine engines, where each level processes and provides output based on lower-level analysis, with feedback mechanisms to modify processing, and methods such as aggregation of state machine outputs, expansion of input busses, and use of difference vectors to reduce data transfer time, allowing for real-time operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hierarchical structure with cascaded finite state machine engines is used to process data, then processing capability and analysis depth are improved, but data transfer time and system complexity increase due to the large and complex state vector that must be passed between engines
Solution Approach 1:
The patent divides the hierarchical structure into multiple levels, where each level processes only the necessary subset of state information. Lower levels handle detailed pattern recognition while higher levels perform abstract analysis, segmenting the data transfer requirements to reduce overall transfer time between engines.
Solution Approach 2:
The patent extracts and transfers only the essential state information between hierarchical levels rather than the complete state vector. By identifying and removing redundant or unnecessary state elements from inter-level communication, the data transfer volume is significantly reduced while maintaining processing effectiveness.
2Productivity
If a hierarchical structure with cascaded finite state machine engines is used to process data, then processing capability and analysis depth are improved, but device complexity increases due to the multiple engines and feedback mechanisms required
Solution Approach 1:
The patent designs the finite state machine engines with universal interfaces and standardized communication protocols that allow them to perform multiple functions across different hierarchical levels. This multi-functionality reduces the need for specialized components at each level, thereby simplifying the overall system architecture despite the increased number of engines.
Solution Approach 2:
The patent implements feedback mechanisms that allow higher levels to adjust processing parameters and guide lower levels based on analysis results. This feedback loop enables the system to adapt dynamically, reducing the need for complex pre-configured processing paths and simplifying the control logic across hierarchical levels.
3Measurement precision
If the complete state vector is passed between finite state machine engines, then processing accuracy is maintained, but data transfer time increases significantly
Solution Approach 1:
The patent extracts only the critical state information necessary for accurate processing at each hierarchical level. By identifying and removing redundant state elements from inter-level communication, the data transfer volume is significantly reduced while maintaining processing effectiveness through selective information transmission.
Solution Approach 2:
The patent implements partial state vector transmission where only the essential subset of state information is passed between levels rather than the complete state vector. This partial action approach maintains sufficient processing accuracy for each level's specific requirements while dramatically reducing data transfer time and bandwidth requirements.
Data Source
AI summary
Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.