Hierarchical Gate Driver Circuit for Display Panels
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Solution Overview
Problem
Conventional gate driver implementations for display panels are hindered by a significant increase in footprint and limited scanning speed due to the need for separate shift register stages for each row of pixel elements, which restricts the flexibility and efficiency of pixel data updates.
Innovation Solution
A hierarchical gate driver circuit that includes a shift register and two groups of gate line drivers, activated based on a periodic clock signal, allowing multiple gate lines to be driven in succession, reducing the number of shift register stages and enabling faster scanning with greater flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each gate line is driven by a different shift register stage, then the gate driver can control each row of pixel elements, but the footprint of the display panel increases significantly
Solution Approach 1:
The gate driver is segmented into multiple independent gate line drivers, each capable of driving a group of gate lines. These drivers are organized in a hierarchical structure where a select line enables specific groups of gate line drivers to activate their associated gate lines simultaneously, reducing the need for continuous shift register stages across the entire panel area.
Solution Approach 2:
The patent introduces a hierarchical control structure with select lines that add a new dimension of control. Instead of a single-dimensional sequential scanning approach, the system uses multi-dimensional control where select lines enable groups of gate line drivers to operate in parallel, effectively organizing the gate driving function in a hierarchical tree structure rather than a linear sequence.
2Ease of operation
If each gate line is driven by a different shift register stage, then the gate driver can select particular rows of pixel elements, but the scanning speed is limited by the time required to drive each row
Solution Approach 1:
The gate driver is divided into multiple independent gate line drivers that can operate simultaneously. Each gate line driver is associated with specific gate lines and can be independently activated by select lines, allowing multiple rows to be driven in parallel rather than sequentially through a single shift register chain.
Solution Approach 2:
Multiple gate line drivers are merged into a hierarchical structure controlled by select lines. When a select line is activated, it enables multiple gate line drivers to work together to drive their respective gate lines simultaneously, combining their capabilities to achieve faster overall scanning speed compared to sequential operation.
3Reliability
If conventional gate driver implementations are used, then each row can be updated with pixel data, but the flexibility and efficiency of pixel data updates are restricted
Solution Approach 1:
The gate driver system is made dynamic through the use of selectable groups of gate line drivers. The select lines enable or disable specific groups of gate line drivers based on the scanning requirements, allowing the system to adapt its operation mode. This dynamic configuration enables flexible updating patterns where different groups of gate lines can be activated simultaneously or sequentially based on the display refresh requirements.
Solution Approach 2:
The hierarchical gate driver structure provides multi-functionality by enabling different scanning patterns and update modes. The same gate driver circuitry can support various pixel data update strategies including sequential scanning, parallel updating of specific row groups, and selective activation based on display content requirements, making the system universally applicable to different display modes and refresh patterns.
Data Source
AI summary
A hierarchical gate driver circuit for an array of pixel elements. The hierarchical gate driver circuit includes a shift register and two or more groups of gate lines drivers. The shift register is configured to activate a plurality of select lines based at least in part on a periodic clock signal. A first group of gate line drivers is configured to drive a plurality of first gate lines, each coupled to a respective row of first pixel elements in the array, when a first select line of the plurality of select lines is activated. A second group of gate line drivers is configured to drive a plurality of second gate lines, each coupled to a respective row of second pixel elements in the array, when a second select line of the plurality of select lines is activated.