Hierarchical Hardware Verification for Data Transformation Components
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Solution Overview
Problem
Formal verification tools face difficulties in solving mathematical problems related to calculating the result of data transformations, particularly when involving sequences or series, leading to inconclusive results and inefficiencies in verifying hardware designs for data transformation components.
Innovation Solution
A hierarchical verification method is employed, representing the hardware design as a set of data transformation components, where leaf components are verified individually and parent components are simplified by replacing child components with abstracted descriptions, allowing formal verification to focus on deterministic causal relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is used to verify hardware design for data transformation components, then verification completeness is improved, but verification time and computational resources increase significantly
Solution Approach 1:
The hardware design is divided into multiple data transformation components organized in a hierarchical structure with parent-child relationships. Each component can be verified independently or in combination with its children, allowing the verification process to be broken down into smaller, more manageable units that reduce overall verification time while maintaining completeness.
Solution Approach 2:
The verification process allows optional verification of individual data transformation components before verifying the complete hardware design. This preliminary verification of sub-components simplifies the overall verification task and can identify issues early, reducing the time required for complete verification.
2Measurement precision
If formal verification is used to verify hardware design for data transformation components, then verification accuracy is improved, but computational complexity increases
Solution Approach 1:
The hierarchical structure segments the hardware design into multiple data transformation components. Each component represents a smaller computational problem that can be solved more efficiently than the complete system, reducing computational complexity while maintaining verification accuracy through systematic composition of results.
Solution Approach 2:
The verification process allows selective verification of subsets of data transformation components rather than requiring complete verification of the entire hardware design. This partial action approach reduces computational complexity by focusing verification resources on critical components or those with higher risk, while still providing meaningful verification accuracy for the verified portions.
3Ease of operation
If simulation-based verification is used to verify hardware design, then ease of operation is improved, but verification completeness deteriorates
Solution Approach 1:
The hierarchical structure enables verification to be performed at multiple levels - individual components, groups of components, or the complete system. This segmentation allows users to choose the appropriate verification scope based on their needs, maintaining ease of operation while improving completeness by systematically covering all components through the hierarchy.
Solution Approach 2:
Individual data transformation components can be verified in advance using simulation-based methods, which are easier to operate. These preliminary verification results are then composed to verify the complete hardware design, improving overall verification completeness while maintaining the ease of operation of simulation-based methods for sub-components.
Data Source
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AI summary
Methods and systems for verifying a hardware design for a main data transformation component. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. The method includes: (a) for each of the plurality of leaf data transformation components, verifying that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions; and (b) for each of the one or more parent data transformation components, formally verifying, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that is configured to for a specific input transaction to the child data transformation component produce a specific output transaction with a causal deterministic relationship to the specific input transaction. During formal verification the formal verification tool is configured to select the specific input transaction and the specific output transaction pair to be each possible valid input transaction and valid output transaction pair for the child data transformation component.