Hierarchical Image Processing Circuit for Line Memory Reduction
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Solution Overview
Problem
The increasing number of pixels in image processing apparatuses for high-definition standards requires larger line memories, leading to increased costs, and existing techniques for reducing line memory capacity through block division result in undesirable processing performance due to increased control periods and total pixels to be processed.
Innovation Solution
An image processing apparatus that divides images into blocks and processes them hierarchically, using enlargement and extraction circuits to manage image layers, reducing the need for large line memories while maintaining processing performance by controlling block sizes and extraction regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels handled by the image processing apparatus is increased to support high-definition standards, then the image quality and resolution are improved, but the capacity of the line memory required increases leading to cost increase
Solution Approach 1:
The image is divided into multiple blocks in the horizontal direction, and processing is performed block by block. This segmentation allows the line memory capacity to be reduced from needing to store the entire image width to only storing a portion corresponding to one block, thereby reducing memory capacity requirements while maintaining high-definition processing capability
Solution Approach 2:
The patent introduces hierarchical layers (first hierarchical layer and second hierarchical layer) to process the image. By creating a reduced-resolution intermediate layer and processing blocks on this layer, the system reduces the dimensional complexity of the original high-resolution image, enabling processing with smaller memory resources
2Ease of manufacture
If the capacity of the line memory is reduced to lower costs, then the manufacturing cost is decreased, but the processing performance deteriorates due to increased number of divided blocks and additional control periods
Solution Approach 1:
By introducing a hierarchical structure with a reduced-resolution second layer, the patent reduces the number of blocks that need to be processed. Blocks on the second hierarchical layer are larger in effective processing units compared to processing the original high-resolution image directly, thereby reducing the total number of control periods required while maintaining cost efficiency
Solution Approach 2:
The patent performs preliminary reduction processing to create the second hierarchical layer before block-by-block processing. This preliminary action of creating a downsampled version allows subsequent block processing to operate on fewer, larger units, reducing the overhead of control periods while maintaining the ability to produce high-quality output
Data Source
AI summary
A first enlargement circuit enlarges an image of a hierarchical layer on a lower side among images of hierarchical layers in which an image of a lower hierarchical layer is a reduced image generated by reducing an image of an upper hierarchical layer. A region extraction circuit extracts a region according to a size of the block of the hierarchical layer on the upper side from a region in the image enlarged by the first enlargement circuit that is at least wider than the block of the hierarchical layer on the upper side. A first hierarchical addition circuit combines an image of the region extracted by the region extraction circuit to the block of the hierarchical layer on the upper side block by block for the blocks.