Hierarchical Interconnect Architecture for NoC Bandwidth Bottlenecks
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Solution Overview
Problem
As the number of cores and intellectual property blocks increases in multi-core processors, traditional network-on-chip (NoC) architectures face challenges in efficiently managing communication bandwidth, leading to potential bottlenecks and inefficiencies in data transfer between processor cores and memory resources.
Innovation Solution
The implementation of a hierarchical interconnect architecture with distributed point-of-access routers and network clusters, allowing for efficient communication between physical layer circuits and network-on-chip circuitry through interconnect structures within the IC die and substrate, facilitating high-bandwidth intra-cluster and inter-cluster communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional 2D mesh interconnect topology is used with routers at edges, then communication between cores is enabled, but bandwidth bottlenecks occur as core count increases to 100-200 cores
Solution Approach 1:
The NoC is divided into multiple network clusters, each with its own dedicated PHY interface and interconnect resources. This segmentation allows independent communication paths for different clusters, eliminating the single bottleneck at the mesh edges and enabling parallel data transfer across multiple clusters simultaneously.
Solution Approach 2:
The patent transitions from a traditional 2D mesh topology to a 2.5D or 3D hierarchical architecture by adding vertical interconnect dimensions through substrate-level routing. This enables direct three-dimensional communication paths between PHY interfaces and NoC clusters, dramatically increasing bandwidth capacity without proportionally increasing interconnect complexity.
2Productivity
If more PHY interfaces are integrated on-die with NoC, then communication efficiency improves, but routing complexity and bandwidth management become more difficult
Solution Approach 1:
Each PHY interface is assigned to a specific network cluster with dedicated routing resources. This segmentation simplifies routing decisions by confining traffic to specific clusters rather than requiring global routing across the entire NoC, reducing routing complexity while maintaining high data transfer efficiency within each cluster.
Solution Approach 2:
Network clusters act as intermediary layers between PHY interfaces and the core NoC fabric. Each cluster manages its own internal routing and traffic arbitration, simplifying the overall routing complexity by distributing control functions to cluster-level intermediaries rather than requiring centralized control for all PHY interfaces.
Data Source
AI summary
Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.