Hierarchical Interconnect Fabric Layout for Lower Routing Congestion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The design of interconnect fabrics in System-on-a-Chip (SoC) with a large number of components faces challenges such as routing congestion, complex placement, and prolonged design cycles due to non-uniform floorplans and high cell counts, which conventional tools struggle to manage effectively.
Innovation Solution
The interconnect fabric is partitioned into smaller sub-fabrics based on physical design information, using hierarchical multiplexing schemes and agglomerative clustering to reduce congestion, with initiators and targets grouped by proximity, and employing 2:1 muxes to optimize wire routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interconnect fabric is designed to connect a large number of on-chip components, then the connectivity and functionality of the SoC are improved, but routing congestion and design complexity increase significantly
Solution Approach 1:
The interconnect fabric is partitioned into multiple smaller sub-fabrics based on physical design information and agglomerative clustering. Each sub-fabric handles a specific group of initiators and targets, reducing the overall complexity of routing while maintaining full connectivity across the SoC. The partitioning is performed using algorithms that consider spatial proximity and communication patterns.
Solution Approach 2:
Different regions of the interconnect fabric are designed with specialized characteristics based on local requirements. Sub-fabrics are optimized for their specific functional domains, with routing resources and multiplexing schemes tailored to the communication patterns of nearby components. This local optimization reduces overall design complexity while maintaining high connectivity.
2Ease of manufacture
If conventional tools are used to manage interconnect fabric design with high cell counts, then the design process follows standard procedures, but routing congestion and design cycle duration increase
Solution Approach 1:
Physical design information is obtained and analyzed before the actual interconnect fabric design. Agglomerative clustering algorithms pre-process the spatial relationships between components to determine optimal sub-fabric partitions. This preliminary action enables subsequent design steps to proceed more efficiently with reduced routing congestion.
Solution Approach 2:
A specialized partitioning algorithm acts as an intermediary between conventional design tools and the interconnect fabric implementation. This intermediary process transforms raw physical design information into optimized sub-fabric configurations, bridging the gap between standard procedures and congestion-free routing.
3Ease of operation
If the interconnect fabric is implemented without partitioning, then the design process is simpler initially, but routing congestion and placement complexity become unmanageable
Solution Approach 1:
The interconnect fabric is divided into manageable sub-fabrics that can be designed and routed independently. This segmentation prevents routing congestion by distributing traffic across multiple smaller networks rather than overwhelming a single large fabric. Each sub-fabric maintains clear and simple placement within its designated region.
Data Source
AI summary
An interconnect fabric in an integrated circuit (IC) device can be hierarchically partitioned into a set of peripheral sub-fabrics and a glue sub-fabric coupled to each of the peripheral sub-fabrics based on the physical design information associated with the IC device. Each of the peripheral sub-fabrics and the glue sub-fabric can be implemented using 2:1 hierarchical multiplexers based on an agglomerative clustering scheme. Physically aware design of the hierarchical multiplexer tree along with the optimal placement of the 2:1 multiplexers can provide smaller overall wire length and reduced routing congestion in the interconnect.