Hierarchical Interrupt Distribution System for Multi-Processor Wiring Reduction
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Solution Overview
Problem
In multi-processor computer systems, the complexity and cost of distributing interrupts increase with the number of processors, especially when they are located on different chips, due to the need for numerous wires and potential differences in clock domains, leading to inefficiencies in chip area and communication delays.
Innovation Solution
A hierarchical interrupt distribution system using logic devices and a shared interrupt bus to route interrupts from redistributors to processing elements, with bus arbitration and clock domain interfaces to synchronize data transfer, and an interchip interface for multi-chip systems to maintain a contiguous interrupt address space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors in a multi-processor system increases, then the processing capability of the system is improved, but the number of wires required for distributing interrupt signals increases and the complexity of appropriately distributing interrupts grows
Solution Approach 1:
The interrupt distribution system is segmented into multiple hierarchical levels with intermediate redistribution devices. Instead of connecting every processor directly to the interrupt source, the system divides the distribution function across multiple stages, where each stage handles a subset of processors. This segmentation reduces the wiring complexity from O(N) to O(log N) where N is the number of processors.
Solution Approach 2:
Intermediate redistribution devices are introduced as mediators between the interrupt source and the processors. These redistribution devices receive interrupt signals and forward them to the appropriate processors, eliminating the need for direct connections between the interrupt source and each processor. This intermediary approach significantly reduces the total number of wires required.
2Adaptability or versatility
If processors are located on different chips in a system, then the system scalability is improved, but the chip area required and the communication delays increase
Solution Approach 1:
The system is divided into multiple chips, each containing a subset of the hierarchical interrupt distribution tree. By segmenting the overall system across multiple chips, each individual chip can be compact in area while the aggregate system achieves high scalability. The hierarchical structure allows each chip to handle local interrupt distribution efficiently.
Solution Approach 2:
The interrupt distribution architecture transitions from a two-dimensional planar layout to a multi-dimensional hierarchical structure. This dimensional change allows the system to organize processors and redistribution devices in multiple levels, enabling efficient distribution across multiple chips while reducing the area requirement on each individual chip.
3Adaptability or versatility
If processors are located on different chips in a system, then the system scalability is improved, but the communication delays in distributing interrupts increase
Solution Approach 1:
The hierarchical distribution structure segments the interrupt path into multiple short hops rather than one long path. By dividing the distribution function across multiple levels, each individual communication hop is minimized, reducing the cumulative delay even as the system scales to more chips and processors.
Solution Approach 2:
The hierarchical structure performs preliminary routing decisions at each level of the distribution tree. Instead of making a single long-distance routing decision, the system makes a series of preliminary routing decisions at intermediate redistribution devices, each optimized for local connectivity. This preliminary action at multiple levels reduces overall communication delay.
Data Source
AI summary
Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.