Hierarchical Interrupt Propagation Scheme for ASICs
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Solution Overview
Problem
As hardware-based application-specific integrated circuits (ASICs) grow in size and complexity, the large number of functional blocks generates numerous interrupt notifications, leading to congestion and increased design and verification efforts due to the need for numerous interconnect wires from blocks to a central interrupt controller, causing errors and timing issues.
Innovation Solution
A hierarchical interrupt propagation scheme organizes slave interrupt handlers in a hierarchical structure, reusing pre-existing interconnect wires and register access interfaces to transmit interrupt packets to a central handler, eliminating the need for dedicated interrupt wires and reducing design and implementation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a central interrupt controller is used to collect interrupt notifications from all functional blocks, then interrupt handling is centralized and coordinated, but the number of interconnect wires increases significantly causing congestion and timing issues
Solution Approach 1:
The patent divides the chip into multiple hierarchical levels with intermediate interrupt controllers at each level. Instead of all functional blocks connecting directly to a single central controller, interrupt notifications are first collected by intermediate controllers at lower levels, which then forward consolidated interrupts to higher-level controllers. This segmentation reduces the number of wires needed at each connection point while maintaining centralized coordination through the hierarchical structure.
Solution Approach 2:
The patent introduces a hierarchical dimension to the interrupt controller architecture, organizing controllers in multiple levels rather than a single flat layer. This dimensional change transforms the wire connectivity from a dense star topology (all blocks to central controller) into a tree-like hierarchical structure, reducing wire congestion at any single point while preserving interrupt handling coordination through the hierarchical control path.
2Quantity of substance
If multiple interconnect wires are run from each functional block to the central interrupt controller, then all interrupt notifications can be transmitted, but frontend RTL development effort and verification complexity increase significantly
Solution Approach 1:
The hierarchical structure segments the interrupt notification collection function across multiple intermediate controllers rather than requiring all notifications to route through a single central controller. Each intermediate controller handles a subset of functional blocks, reducing the complexity of wire management and RTL development at any single controller while collectively maintaining full interrupt notification capacity through the hierarchical aggregation.
3Quantity of substance
If too many interconnect wires converge on the central interrupt controller, then all interrupt notifications can be received, but backend layout time and effort increase significantly to meet timing requirements
Solution Approach 1:
The patent segments the wire convergence points across multiple intermediate controllers distributed throughout the chip hierarchy. Instead of all wires converging at a single central controller creating a bottleneck, the hierarchical structure distributes wire connections across multiple levels and locations, reducing the layout complexity and timing closure effort at any single convergence point while maintaining full interrupt notification reception capability through the hierarchical path.
Solution Approach 2:
By introducing hierarchical levels, the patent distributes wire convergence across multiple spatial and organizational dimensions rather than concentrating all wires at a single point. This dimensional distribution reduces backend layout complexity and timing requirements at any single controller while preserving the ability to receive all interrupt notifications through the hierarchical control structure.
Data Source
AI summary
A new approach of systems and methods to support a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling is proposed. The hierarchical interrupt propagation scheme organizes a plurality of slave interrupt handlers associated functional blocks in a chip in a hierarchy. When an exception or error condition occurs in a functional block, a slave interrupt handler associated with the functional block creates an interrupt packet as an interrupt notification and utilizes pre-existing input and output interfaces that have already been utilized for accessing registers of the functional block to transmit the created interrupt packet to a central interrupt handler through the hierarchy without running dedicated interconnect wires out of the functional block. The central interrupt handler then processes the interrupt notifications and provides a response packet to the interrupt notification back to slave interrupt handler that created the interrupt packet to configure or adjust the functional block accordingly.