Hierarchical JTAG Scan Path for Fast Semiconductor Testing
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Solution Overview
Problem
Current JTAG systems face limitations in efficiently accessing and testing embedded instrumentation within semiconductor devices, particularly in terms of speed and security, due to complex network hierarchies and the need for secure access to sensitive IP cores.
Innovation Solution
The implementation of a hierarchical JTAG scan path using a Test Access Port (TAP) controller and Segment-Insertion-Bit circuits (SIBs) arranged in multiple hierarchy levels, with root-SIBs that can be configured to route or disconnect the test bus, allowing for fast and secure data streaming and instruction execution across the network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hierarchical JTAG network structure is used to access embedded instrumentation, then the ability to test complex semiconductor devices is improved, but the access speed and testing efficiency deteriorate due to multiple hierarchy levels
Solution Approach 1:
The network is divided into multiple hierarchy levels with root-SIBs at each level. This segmentation allows the test bus to be selectively opened or closed at different hierarchy levels, enabling fast access to specific instrument groups while maintaining the ability to test the entire complex network structure.
Solution Approach 2:
The root-SIBs are configured to dynamically switch between Open and Closed states based on testing requirements. When a root-SIB is opened, it allows fast passage of the test bus through that hierarchy level, significantly improving access speed for instruments behind that root-SIB while maintaining network security and structure.
2Reliability
If secure access control is implemented for sensitive IP cores, then security is improved, but the complexity of access control mechanisms increases
Solution Approach 1:
The network is segmented into multiple hierarchy levels with root-SIBs that can be independently controlled. Each root-SIB acts as an access control point that can be opened or closed based on security requirements, providing granular control over access to sensitive IP cores without requiring a complex centralized control mechanism.
Solution Approach 2:
The root-SIBs serve as intermediary elements between the TAP controller and the embedded instrumentation. They provide a controlled access point that can be selectively opened to allow test bus passage to authorized instruments while blocking unauthorized access, simplifying the overall security architecture.
3Adaptability or versatility
If multiple hierarchy levels of SIBs are used to organize the test network, then the organization and security of the network is improved, but the number of clock cycles required for access increases
Solution Approach 1:
The root-SIBs are configured to dynamically switch between Open and Closed states. When opened, they allow the test bus to pass through multiple hierarchy levels in a single continuous stream, dramatically reducing the number of clock cycles required for access while maintaining the organized hierarchical structure for security and manageability.
Solution Approach 2:
The root-SIBs are pre-configured with control logic that allows them to be rapidly opened in response to specific test requests. This preliminary configuration enables fast access by eliminating the need to sequentially navigate through each hierarchy level, reducing access time while preserving network organization.
Data Source
AI summary
An IC includes testing circuitry including a Test Access Port (TAP) controller and Segment-Insertion-Bit circuits (SIBs) arranged in multiple hierarchy levels. Some of the SIBs are connected to hardware units, and some of the SIBs are root-SIBs that connect between neighbor hierarchy levels. A test bus runs in a daisy-chained loop path starting at the TAP controller, passing via at least some of the SIBs and ending at the TAP controller. Each root-SIB has an Open state and a Closed state. The TAP controller, for a selected subset of the hardware units that are to be tested, selects one or more root-SIBs that, when set to the Open state, make the selected subset of hardware units reachable by the test bus, and sends via the daisy-chained test bus a data stream comprising one or more instructions that set two or more of the selected root-SIBs to the Open state.