Hierarchical Memory Controller for Bandwidth and Power Scaling
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Solution Overview
Problem
Existing memory technologies face challenges in achieving better performance, lower power consumption, and increased memory density due to non-linear power increase and decreasing improvements from generation to generation, with limited exploration of fine-grained optimizations and memory controller co-optimization.
Innovation Solution
A hierarchical memory controller architecture is introduced, dividing the memory controller into a leader and follower controller, where the leader manages request ordering and scheduling, while the follower executes specific memory commands, allowing for decoupling and optimization of memory technologies such as 3D stacked DRAM and FeRAM, and enabling efficient command bus sharing and scalable designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory technology is optimized independently as a macrocell or for specific applications, then application-specific performance is improved, but fine-grained optimizations with logic technology and architecture are not achieved
Solution Approach 1:
The memory system is divided into multiple memory banks (first memory bank, second memory bank) that can be independently accessed. The controller is segmented into multiple channels (first channel, second channel) that can simultaneously access different memory banks, enabling fine-grained parallelism and optimization without requiring complete integration with logic technology.
2Speed
If standard DDR memory is used, then compatibility is maintained, but bandwidth for high-performance applications like graphics is insufficient
Solution Approach 1:
The memory system dynamically adapts to different application requirements by providing multiple memory banks that can be selectively accessed through different channels. The controller can dynamically allocate resources and adjust access patterns based on workload characteristics, achieving high bandwidth for graphics applications while maintaining compatibility with standard DDR protocols for other applications.
3Quantity of substance
If memory density is increased from generation to generation, then storage capacity is improved, but power consumption increases non-linearly
Solution Approach 1:
The memory system is divided into multiple independent memory banks that can be selectively accessed. This segmentation allows the system to activate only the necessary memory banks based on workload requirements, reducing unnecessary power consumption while maintaining high memory density. The controller can put idle memory banks into low-power states, addressing the non-linear power increase problem.
4Device complexity
If a single monolithic memory controller is used, then control logic is simplified, but scalability and flexibility for advanced packaging options are limited
Solution Approach 1:
The memory controller is divided into multiple independent channels (first channel, second channel) that can simultaneously access different memory banks. This segmented architecture provides scalability and flexibility for advanced packaging options like 3D stacking, where memory controllers can be distributed across multiple dies or layers while maintaining simplified control logic within each channel.
Data Source
AI summary
An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.