Hierarchical Memory Architecture with Concentrator Device
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Solution Overview
Problem
Current microprocessor systems face performance bottlenecks due to power dissipation at the input/output interface during data transmission between the CPU and system memory, primarily attributed to intrinsic capacitances of system-level buses, necessitating simultaneous power and timing optimization.
Innovation Solution
A hierarchical memory architecture is implemented using a concentrator device that separates memory devices from the Front Side Bus, reducing intrinsic capacitance and enabling high-speed communication through a concentrator device with features like Phase-Change Memory (PCM) arrays, Magnetic Random Access Memory (MRAM), and Content Addressable Memory (CAM), along with error correction and data compression, to optimize memory access and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is transmitted between CPU and system memory through system-level buses, then data transmission function is achieved, but power dissipation increases due to intrinsic capacitances
Solution Approach 1:
The patent segments the memory system into multiple hierarchical levels (L1, L2, L3 caches and main memory), separating frequently accessed data from less frequently accessed data. This segmentation allows the CPU to access hot data in low-latency L1/L2 caches without triggering high-power transactions on the full system bus, thereby reducing overall power dissipation while maintaining system performance.
Solution Approach 2:
The patent introduces intermediary cache structures (L1, L2, L3 caches) between the CPU and main memory. These intermediaries buffer data transfers, allowing the CPU to access data in fast local caches without directly activating the high-capacitance system bus for every memory access, thus reducing power dissipation at the CPU I/O interface while maintaining high productivity.
2Speed
If system-level buses are used for memory access, then data transmission is enabled, but bus latency increases
Solution Approach 1:
The patent divides the unified memory space into hierarchical segments (L1, L2, L3 caches and main memory) with progressively increasing access times. Frequently accessed data is kept in faster L1/L2 segments, reducing the average memory access latency and eliminating the need for slow system bus transactions for hot data, thereby improving speed without significant time loss.
Solution Approach 2:
The patent adds a temporal dimension to memory hierarchy by organizing memory into levels with different access speeds and latencies. This dimensional organization allows the system to serve different data access patterns at appropriate speeds, reducing average latency by serving hot data from fast L1/L2 caches rather than waiting for slow system bus transactions.
3Ease of operation
If memory devices are directly connected to Front Side Bus, then data access is simplified, but intrinsic capacitance increases causing power and timing issues
Solution Approach 1:
The patent segments the memory subsystem into hierarchical levels with dedicated controllers for each level. This segmentation allows simple access patterns for L1/L2 caches managed by dedicated cache controllers, while main memory accesses through the FSB only occur when necessary, reducing the frequency and power of FSB transactions while maintaining ease of operation through unified memory management.
Solution Approach 2:
The patent introduces cache controllers and memory management units as intermediaries between the CPU and main memory devices. These intermediaries handle data access requests, caching operations, and protocol conversion, simplifying CPU operations while reducing direct FSB transactions and associated power dissipation at the I/O interface.
Data Source
AI summary
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.