Hierarchical Leader-Follower Controllers for Flexible Memory Access
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Solution Overview
Problem
Existing memory technologies face challenges in achieving better performance, lower power consumption, and increased memory density due to limitations in memory controller design and co-optimization with logic technology, leading to memory bottlenecks in data processing systems.
Innovation Solution
A hierarchical memory controller architecture is introduced, dividing the memory controller into a leader and follower controller, where the leader controller schedules requests and the follower controller issues commands, allowing for decoupling and optimization of memory access without specific knowledge of the memory type, enabling efficient use of emerging memory technologies like 3D stacked DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory controller design is optimized independently as a macrocell, then memory performance is improved for specific applications, but device complexity increases and adaptability to different memory types decreases
Solution Approach 1:
The memory controller is divided into two separate components: a host-side leader controller that handles scheduling and command generation, and a memory-side follower controller that manages memory-specific operations. This segmentation allows each controller to be optimized for its specific function, reducing overall complexity while maintaining high performance.
Solution Approach 2:
The leader controller is designed with memory-type-agnostic scheduling logic that can work with various memory technologies (HBM, GDDR, DDR, FeRAM, MRAM, PCM, ReRAM) without requiring specific knowledge of each memory type, making the system universally applicable across different memory technologies.
2Productivity
If memory technology is optimized for specific applications like DNN, then performance for those applications is improved, but adaptability to other applications and memory types is reduced
Solution Approach 1:
The hierarchical controller architecture enables a single system to support multiple memory technologies (HBM, GDDR, DDR, FeRAM, MRAM, PCM, ReRAM) and various applications (DNN, graphics, general-purpose computing) through the leader controller's universal scheduling logic combined with follower controllers' memory-specific optimizations.
Solution Approach 2:
The system dynamically adapts to different memory types and application requirements by having the leader controller generate memory-type-agnostic schedules that are then executed by follower controllers configured for specific memory technologies, allowing the system to be reconfigured for different workloads without hardware changes.
3Use of energy by moving object
If non-linear power increase is addressed through generation-to-generation improvements, then power efficiency is improved, but productivity gains are reduced due to memory bottlenecks
Solution Approach 1:
By separating the controller functions into leader and follower components, the system achieves better power efficiency through specialized optimization of each part while maintaining high memory bandwidth, preventing the memory bottleneck that would otherwise limit productivity gains from power efficiency improvements.
4Quantity of substance
If memory density is increased through advanced packaging, then quantity of memory is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The hierarchical controller architecture works seamlessly with advanced packaging technologies by dividing control functions across separate controller components that can be implemented in different locations (host-side and memory-side), accommodating high-density memory configurations without increasing overall system complexity.
Data Source
AI summary
An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.