Hierarchical Memory Mapping for PLD Embedded Block RAM Efficiency
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Solution Overview
Problem
Conventional memory mapping techniques in programmable logic devices (PLDs) often result in inefficient utilization of embedded block RAMs (EBRs), requiring more resources than necessary and leaving unutilized portions, when mapping user-specified memories that exceed the size of a single EBR.
Innovation Solution
Implementing a hierarchical slicing and mapping method that divides user-defined logical memories into main and subareas, allowing for flexible mapping onto EBRs with different depth-width configurations, and using programmable logic blocks (PLBs) to balance resource utilization, thereby optimizing the use of EBRs and other PLD resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional memory mapping techniques are used to map user-specified memories to EBRs, then the mapping process is simple, but the utilization of EBRs is inefficient and more EBRs are required than necessary
Solution Approach 1:
The patent divides the logical memory into multiple slices, each of which can be independently mapped to EBRs. This segmentation allows for more flexible and efficient utilization of EBR resources by distributing memory mapping across multiple smaller units rather than attempting to map the entire logical memory to a single EBR or using a rigid conventional mapping approach.
Solution Approach 2:
The patent introduces a new dimension to memory mapping by considering both depth and width configurations of EBRs simultaneously. Instead of conventional single-dimension mapping, the invention explores multiple depth-width configuration combinations to find the optimal mapping that minimizes the number of EBRs required while maximizing utilization efficiency.
2Ease of manufacture
If conventional memory mapping techniques are used, then the mapping process is straightforward, but unutilized portions are left in EBRs resulting in wasted area
Solution Approach 1:
The patent systematically varies the depth and width parameters of EBR configurations to find the optimal mapping. By changing these parameters and evaluating different combinations, the invention identifies mappings that fully utilize EBR capacity without leaving unutilized portions, thereby eliminating wasted area while maintaining a manageable mapping process.
Solution Approach 2:
The patent employs a dynamic mapping approach where the EBR depth-width configurations are not fixed but are selected and adjusted based on the specific requirements of the logical memory being mapped. This dynamic selection process allows the mapping to adapt to different memory sizes and patterns, ensuring optimal utilization and eliminating wasted area in EBRs.
3Quantity of substance
If hierarchical slicing and mapping is implemented to optimize EBR utilization, then memory area efficiency is improved, but the complexity of the mapping process increases
Solution Approach 1:
By dividing logical memory into hierarchical slices, the patent transforms a complex single-step mapping problem into multiple simpler sub-mapping problems. Each slice can be independently mapped to EBRs using standardized procedures, which reduces the overall complexity compared to attempting to map the entire logical memory in one complex operation while still achieving optimal EBR utilization.
Solution Approach 2:
The hierarchical slicing approach adds a structural dimension to the mapping process, organizing memory mapping in layers or levels. This dimensional organization provides a systematic framework that manages complexity by breaking down the mapping task into hierarchical stages, making the process more tractable while enabling sophisticated optimization of EBR depth-width configurations.
4Quantity of substance
If EBRs are configured in multiple depth-width configurations to improve mapping efficiency, then resource utilization is optimized, but the difficulty of configuration and management increases
Solution Approach 1:
The patent systematically explores different depth-width parameter combinations of EBRs and establishes a methodology for selecting the optimal configuration for each mapping scenario. By creating a structured approach to parameter selection and evaluation, the invention makes it easier to manage multiple configurations rather than treating them as arbitrary options, thereby optimizing utilization while simplifying the configuration process.
Solution Approach 2:
The patent implements mechanisms where the mapping system automatically selects and configures appropriate EBR depth-width configurations based on the characteristics of the logical memory being mapped. This self-service approach reduces the manual burden of configuration by enabling the system to autonomously determine optimal settings, thereby maintaining high utilization efficiency while improving ease of operation.
Data Source
AI summary
Various techniques are provided to implement a logical memory in programmable logic devices (PLDs) having embedded block RAMs (EBRs). For example, a computer-implemented method includes determining a main area of a logical memory that can be fully mapped to a first one or more EBRs configured in a first depth-width configuration, mapping the main area to the first one or more EBRs, and mapping the remainder of the logical memory to a second one or more EBRs configured in a second or more depth-width configurations. The mapping of the remainder of the logical memory may be performed hierarchically by a recursive process, in some embodiments. The depth-width configurations and the corresponding mapping may be selected according to an efficiency metric, for example. Other embodiments include a system comprising a PLD and a configuration memory storing configuration data generated by such a method, and a PLD configured with such configuration data.