Hierarchical Memory Systems With Logic Circuitry On Persistent Memory
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Solution Overview
Problem
Existing hierarchical memory systems rely heavily on volatile memory, leading to increased costs and limitations in scaling to meet growing demand for computing resources, especially in multi-user networks where additional users are turned away due to memory resource constraints.
Innovation Solution
The implementation of a hierarchical memory system with logic circuitry resident on a persistent memory device, allowing data to be stored and retrieved from non-volatile memory resources using interfaces typically reserved for volatile memory, thereby reducing latency and increasing available memory resources at a lower cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hierarchical memory systems rely heavily on volatile memory, then memory access speed is improved, but system cost increases and scalability is limited
Solution Approach 1:
The memory system is segmented into multiple hierarchical levels including volatile memory (DRAM) for fast access and non-volatile memory (NAND flash) for bulk storage. The memory controller divides memory management into distinct functional blocks including address latches, page buffer controllers, and wear leveling managers, allowing each segment to operate independently at its optimal performance level.
Solution Approach 2:
The patent introduces a vertical hierarchical dimension to the memory architecture, stacking volatile and non-volatile memory layers with intelligent controllers. This multi-dimensional approach allows the system to access frequently used data in the fast volatile layer while maintaining large capacity in the non-volatile layer, effectively resolving the speed-capacity tradeoff.
2Quantity of substance
If more volatile memory is provided to meet growing demand, then memory resource availability is improved, but system cost increases
Solution Approach 1:
The patent implements a logical copy mechanism where data is replicated across volatile and non-volatile memory layers with intelligent management. The memory controller maintains logical address mappings that allow the system to present a unified memory space to the processor while physically distributing data across different memory technologies with different cost structures.
Solution Approach 2:
The system dynamically changes operational parameters including memory allocation policies, cache replacement strategies, and wear leveling thresholds based on workload characteristics. This allows the memory subsystem to adapt to different access patterns and optimize the balance between performance and cost for varying application requirements.
3Quantity of substance
If data is stored in non-volatile memory, then storage capacity is improved, but data access latency increases
Solution Approach 1:
The memory controller performs preliminary actions by pre-fetching data from non-volatile memory to volatile cache layers before actual access is needed. It also performs wear leveling operations in advance to distribute write cycles evenly across flash memory blocks, preventing premature degradation and maintaining long-term reliability without sacrificing access performance.
Solution Approach 2:
The patent introduces volatile memory layers and intelligent controllers as intermediaries between the processor and non-volatile storage. This intermediary architecture allows the system to maintain large non-volatile capacity while presenting fast volatile memory access characteristics to the processor, effectively masking the inherent latency of non-volatile memory through buffering and caching mechanisms.
Data Source
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AI summary
Apparatuses, systems, and methods corresponding to hierarchical memory systems are described. Logic circuitry can be resident on a persistent memory device, thereby reducing latencies associated with transferring data between the logic circuitry and the persistent memory device. Logic circuitry on a persistent memory device may include an address register configured to store logical addresses corresponding to stored data. The logic circuitry may receive a redirected request (e.g., prior to redirection, directed to a non-persistent memory device) to retrieve a portion of the data stored in the persistent memory device, determine, in response to receipt of the request to retrieve the portion of the stored data, a physical address corresponding to the portion of the data based on the logical address stored in the address register, and cause the data to be retrieved from the persistent memory device.