Hierarchical Memory System Using Persistent Storage

The patent segments the memory system into multiple levels: volatile memory (DRAM) for frequently accessed data and non-volatile memory (NAND flash) for less frequently accessed data. The memory controller divides memory management tasks between these segments, allowing the system to leverage the speed of volatile memory while utilizing the large capacity of non-volatile memory, thereby resolving the contradiction between access speed and memory capacity.

The patent introduces a hierarchical dimension to the memory system by stacking volatile and non-volatile memory layers. Instead of treating memory as a single uniform resource, the system creates a multi-dimensional memory architecture where data can be stored at different levels based on access frequency, enabling both fast access for critical data and large capacity for bulk storage.

The patent implements preliminary actions by pre-loading frequently accessed data from non-volatile memory into volatile memory buffers before they are needed. The memory controller predicts access patterns and proactively transfers data to faster storage locations, ensuring that when data is actually accessed, it is already in high-speed memory, thus maintaining performance while using non-volatile memory for bulk storage.

The patent introduces volatile memory buffers and a sophisticated memory controller as intermediaries between non-volatile memory and the CPU. These intermediaries cache data from non-volatile memory and manage transfer operations, shielding the CPU from the non-deterministic access times of non-volatile memory while still enabling large capacity storage.