Hierarchical Memory System Pseudo-Bank Emulation
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Solution Overview
Problem
Conventional techniques fail to effectively connect and manage different memory technologies in a hierarchical manner, making it difficult to create a unified memory space that addresses varying latencies and bandwidths required for memory access operations.
Innovation Solution
A hierarchical memory system is implemented, where slower memory technologies are positioned behind faster ones, using pseudo-banks to emulate fast memory banks and reduce latency overhead through pre-fetching, data prediction, and timing feedback, allowing multiple memory types to appear as a single unified memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional techniques are used to connect different memory types, then memory capacity can be extended, but it is difficult to create a unified memory space that addresses varying latencies and bandwidths
Solution Approach 1:
The patent introduces controller C1 as an intermediary between controller C0 and memory segment M1. Controller C1 includes pseudo-banks that emulate fast memory banks, acting as a mediator that translates between the fast memory interface expected by controller C0 and the slower actual memory technology in segment M1. This intermediary resolves the contradiction by enabling capacity extension while maintaining a unified memory space appearance through the pseudo-bank emulation layer.
Solution Approach 2:
The patent implements a nested hierarchical structure where controller C0 contains controller C1, which in turn contains memory segment M1. The pseudo-banks are nested within controller C1, creating a nested doll-like hierarchy where each layer provides different functionality. This nesting enables the system to present a unified memory space at the outer layer while containing specialized memory management capabilities at inner layers, resolving the complexity issue.
2Quantity of substance
If slower memory technologies are used to increase capacity, then memory capacity increases, but latency increases
Solution Approach 1:
The patent implements pre-fetching mechanisms where controller C1 anticipates memory access needs and pre-loads data into the pseudo-banks before actual access requests arrive. By performing preliminary actions of data preparation and caching in the pseudo-bank layer, the system reduces the effective latency experienced by controller C0, even though the underlying memory technology is slower. This resolves the contradiction between capacity and latency.
Solution Approach 2:
The patent creates copies of memory data in the pseudo-banks within controller C1. Instead of directly accessing the slower memory segment M1, controller C0 accesses copied data in the pseudo-banks, which emulate fast memory characteristics. This copying mechanism allows the system to provide fast access paths for frequently accessed data while maintaining the capacity benefits of slower high-capacity memory technologies, thus resolving the latency-capacity contradiction.
3Productivity
If multiple memory types are integrated in a hierarchical manner, then bandwidth and capacity are enhanced, but it is difficult to manage communication and access operations
Solution Approach 1:
The patent designs controller C1 to perform multiple functions: it manages the slower memory segment M1, emulates fast memory banks through pseudo-banks, handles translation between different memory interfaces, and provides both caching and data movement functionality. This multi-functionality consolidates complex hierarchical management into a single controller that appears universal to upper layers, making memory access operation management easier while maintaining enhanced bandwidth and capacity.
Solution Approach 2:
The patent segments the memory system into distinct functional units: controller C0 for fast access management, controller C1 for hierarchical coordination, memory segment M0 for fast memory, and memory segment M1 for high-capacity slower memory. Each segment has specialized responsibilities, and the segmentation is managed through a unified interface at controller C1. This segmentation enables enhanced bandwidth through parallel operations in different segments while simplifying management by assigning specific roles to each segment.
Data Source
AI summary
A method and apparatus of performing a memory operation includes receiving a memory operation request at a first memory controller that is in communication with a second memory controller. The first memory controller forwards the memory operation request to the second memory controller. Upon receipt of the memory operation request, the second memory controller provides first information or second information depending on a condition of a pseudo-bank of the second memory controller and a type of the memory operation request.