Hierarchical Memory Architecture with Redundant Sub-Arrays
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Solution Overview
Problem
Conventional memory devices face challenges in increasing bandwidth without significant increases in power consumption, area, or circuit complexity, and struggle with efficiently substituting defective memory resources, which can slow down memory access.
Innovation Solution
The proposed solution involves a hierarchical memory architecture where main data lines extend over memory sub-arrays and main column-select lines route over the narrow spaces between them, allowing for greater data widths and efficient resource substitution using row-address signals to identify and replace defective resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory bandwidth is increased by accessing more data bits in parallel, then bandwidth is improved, but power consumption and area requirements dramatically increase
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own sense amplifiers and data lines. This segmentation allows parallel access to multiple sub-arrays simultaneously, increasing bandwidth without requiring a single massive data path that would consume excessive power and area.
Solution Approach 2:
The patent introduces a hierarchical structure with main data lines extending over sub-arrays and local data lines within sub-arrays. This multi-dimensional routing architecture enables parallel data paths through different spatial dimensions, achieving higher bandwidth without linearly increasing power consumption.
2Reliability
If redundant columns are substituted for defective memory resources, then reliability is improved, but access time increases due to substitution delay
Solution Approach 1:
Redundant columns are pre-configured and physically positioned adjacent to defective columns. The substitution mechanism is prepared in advance, allowing defective columns to be replaced by adjacent redundant columns without requiring time-consuming data transfer from distant locations, thus maintaining fast access times while ensuring reliability.
Solution Approach 2:
The patent introduces column selection circuitry and multiplexing mechanisms that act as intermediaries between defective columns and redundant columns. These intermediaries enable seamless substitution by routing data through alternative paths without requiring direct intervention or complex reconfiguration during memory access operations.
3Reliability
If repair circuitry is added to substitute defective columns, then reliability is improved, but device complexity increases
Solution Approach 1:
The repair circuitry is merged with the existing column selection and control logic. The same circuitry that selects columns for normal operation is extended to also handle redundant column selection, eliminating the need for separate repair circuits and reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The column selection circuitry is designed to serve multiple functions: selecting columns for normal memory operations and selecting redundant columns for defect substitution. This multi-functional design reduces the need for dedicated repair circuits, thereby lowering device complexity while ensuring reliable defect compensation.
Data Source
AI summary
A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.