Hierarchical Memory Modules with Volatile Cache and Nonvolatile Storage

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Solution Overview

Problem

Existing memory technologies exhibit varying performance, durability, density, cost, and power consumption, with some technologies having short latency for read access but longer write times and limited write operations, making them unsuitable for certain applications, and differing in voltage and current usage leading to different power consumption rates.

Innovation Solution

A hierarchical memory system is implemented, utilizing a combination of volatile and non-volatile integrated circuit memory devices in different hierarchies, where volatile devices act as a read/write cache and non-volatile devices store data, optimizing write operations and reducing power consumption by using a daisy chain configuration and buffer ICs to manage data transfer and remapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If volatile memory devices are used for fast read/write access, then read latency is reduced, but power consumption increases

Engineering Contradiction:
Improveread latencyVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The memory system is segmented into multiple hierarchies (first hierarchy with volatile memory devices, second hierarchy with non-volatile memory devices). This segmentation allows the system to use fast volatile memory for frequently accessed data while using energy-efficient non-volatile memory for less frequently accessed data, thereby reducing overall power consumption while maintaining fast read latency for critical operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different memory technologies are assigned to different hierarchical levels based on their local quality characteristics. Volatile memory devices with fast access speeds are placed in the first hierarchy for high-speed operations, while non-volatile memory devices with lower power consumption are placed in the second hierarchy. This local quality assignment optimizes both read latency and power consumption for different data access patterns.

Inventive Principle:
Principle #3Local quality

2Reliability

If non-volatile memory devices are used for data storage, then write data durability is increased, but write operation speed decreases

Engineering Contradiction:
Improvewrite data durabilityVSAvoidwrite operation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

Write operations are performed preliminarily in the first hierarchy using volatile memory devices, which provide fast write speeds. The data is then transferred to the second hierarchy using non-volatile memory devices for durable long-term storage. This preliminary action in the fast volatile memory allows the system to achieve both fast write operation speeds and high write data durability through the hierarchical approach.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The first hierarchy with volatile memory devices acts as an intermediary between the controller and the second hierarchy with non-volatile memory devices. This intermediary layer buffers and manages data transfer, allowing fast write operations to be performed in the volatile memory while simultaneously transferring data to the non-volatile memory for durable storage, thus resolving the contradiction between write speed and durability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If high-density memory devices are used, then storage capacity is increased, but manufacturing cost increases

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The memory system employs multiple types of memory devices (volatile and non-volatile) that serve different functions within the same system. This multi-functionality allows the system to achieve high storage capacity through the combination of different memory technologies while leveraging the cost advantages of non-volatile memory devices for bulk storage, thereby reducing overall manufacturing cost compared to using only high-density volatile memory.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Device complexity

If a single memory technology is used, then device complexity is reduced, but system performance is limited

Engineering Contradiction:
Improvememory system structureVSAvoidsystem performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The memory system dynamically manages data across multiple hierarchies based on access patterns and performance requirements. The controller intelligently determines when to transfer data between the first hierarchy (volatile memory) and second hierarchy (non-volatile memory), allowing the system to adapt to different workload conditions. This dynamic management enables high system performance while maintaining relatively simple device complexity through unified control mechanisms.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11823757B2System including hierarchical memory modules having different types of integrated circuit memory devices
Publication Date: 2023.11.21 RAMBUS INC
  • US11823757B2 patent drawing
  • US11823757B2 patent drawing
  • US11823757B2 patent drawing

AI summary

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.