Hierarchical Memory with Virtual Warm-Page Buffering

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Solution Overview

Problem

Existing computing systems face inefficiencies due to repeated promoting and demoting of data between fast and slow memory tiers, leading to significant overhead and performance degradation from 'warm' pages with intermediate access frequencies.

Innovation Solution

Implementing an intermediate memory zone within the slow memory, allowing data to be virtually promoted or demoted without physical relocation, and dynamically adjusting its size based on access patterns to minimize repeated migrations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data is frequently promoted and demoted between fast and slow memory tiers, then memory utilization is optimized, but computational overhead and performance degradation increase due to repeated data transfers

Engineering Contradiction:

Improvememory utilization optimizationVSAvoidsystem performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces an intermediate memory zone as a buffer between fast and slow memory tiers. This intermediate zone receives data during promotion operations and supplies data during demotion operations, acting as a mediator that reduces the frequency of direct data transfers between fast and slow memory. By caching data in this intermediate zone, the system optimizes memory utilization while minimizing the computational overhead of repeated migrations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If an intermediate memory zone is introduced to reduce repeated migrations, then system performance improves, but device complexity increases

Engineering Contradiction:

Improvesystem performanceVSAvoidmemory hierarchy structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the intermediate memory zone with the existing slow memory structure, positioning it as a virtual zone within slow memory rather than a completely separate physical component. This integration approach allows the intermediate zone to leverage the existing memory infrastructure while providing the additional functionality of reducing migration overhead, thereby improving system performance without proportionally increasing device complexity.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If the intermediate memory zone size is dynamically adjusted, then memory utilization is optimized, but control complexity increases

Engineering Contradiction:

Improvememory utilizationVSAvoidzone size management

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic size adjustment of the intermediate memory zone based on system conditions such as memory pressure and access patterns. The zone size can be expanded when more data needs to be cached to reduce migrations, and contracted when less data is needed to optimize utilization. This dynamic adaptability allows the system to optimize memory utilization while managing the complexity through automated, condition-based adjustments.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12505049B2Hierarchical memory system

Publication Date: 2025.12.23 SAMSUNG ELECTRONICS CO LTD

AI summary

A hierarchical memory system and method. In some embodiments, the method includes: demoting a first page of data from a fast memory to a slow memory; promoting the first page of data from the slow memory to an intermediate memory zone; and promoting the first page of data from the intermediate memory zone to the fast memory, wherein the intermediate memory zone includes a virtual zone within the slow memory.