Hierarchical Microchannel Cooling With Multi-Level Hard Mask Etching
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Solution Overview
Problem
Conventional cleanroom techniques struggle to create fully 3D multi-level, hybrid, hierarchical microchannel structures due to limitations in achieving uniform photoresist coating and multiple-depth etching, leading to unsatisfactory coating and etching issues, which hinder the fabrication of complex microfluidic and cooling devices.
Innovation Solution
An unconventional process flow using Silicon Oxide as an etch mask layer, allowing multiple rounds of lithography and deep Si etching to create hierarchical multi-level structures, enabling the transfer of patterns from the SiO layer to Silicon with improved selectivity and reduced steps, thus overcoming the limitations of conventional lithography-based methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional cleanroom techniques with photoresist masking are used, then simple 2D or shallow 3D structures can be fabricated, but fully 3D multi-level hierarchical structures with high aspect ratios cannot be created due to non-uniform coating and multiple-depth etching limitations
Solution Approach 1:
The patent introduces silicon oxide as an intermediary hard mask layer between the photoresist and the silicon substrate. This intermediary layer enables multiple rounds of lithography and etching to create complex 3D hierarchical structures, as it provides a stable platform for repeated patterning operations that cannot be achieved with photoresist alone on etched surfaces
Solution Approach 2:
The fabrication process is segmented into multiple discrete lithography and etching rounds, each creating a specific level of the hierarchical structure. The silicon oxide mask is deposited and patterned separately for each depth level, allowing precise control over the multi-level geometry without the coating uniformity problems that would arise from attempting to create all levels in a single step
2Temperature
If channel dimensions are reduced to increase heat transfer coefficient, then thermal performance improves, but pressure drop increases at a much faster rate
Solution Approach 1:
The patent transitions from 2D planar cooling channels to 3D hierarchical microchannel structures with multiple depth levels. This dimensional change allows the coolant to access heat transfer surfaces at different heights, effectively increasing the heat transfer coefficient without requiring further reduction in channel width, thereby avoiding the exponential increase in pressure drop
Solution Approach 2:
The hierarchical structure nests smaller microchannels within larger channels at multiple depth levels. This nested arrangement allows efficient heat transfer from heat sources at different depths while maintaining adequate channel dimensions to avoid excessive pressure drop, as each nested level serves a specific thermal management function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reliable fabrication of 3D hierarchical features with high aspect ratios and tall structures up to 400-500 um, reducing costs and increasing throughput, while allowing for more complex designs and improved thermal performance in microfluidics and cooling technologies.
Implementation Method 1
Deposit Silicon Oxide on the wafer—CVD (Chemical Vapour Deposition) or HDPECVD (High Density Plasma Enhanced CVD) process is used to deposit a 1-2 um layer of Silicon Oxide (SiO) on a bare Silicon wafer. This acts as a hard mask during the Deep Silicon Etching.
Implementation Method 2
Exposure of design to pattern the PR and development of exposed features—Next, UV light of appropriate wavelength, energy and distance is used to expose the design layer on the PR (this selectively changes the chemical composition of the PR and makes it soluble in the developer solvent)
Implementation Method 3
Deposit Silicon Oxide on the wafer—CVD (Chemical Vapour Deposition) or HDPECVD (High Density Plasma Enhanced CVD) process is used to deposit a 1-2 um layer of Silicon Oxide (SiO) on a bare Silicon wafer
Implementation Method 4
Coating Photoresist (PR) on the wafer—When PR is puddle dispensed at the center of a Silicon wafer spinning at a high RPM, it spreads radially outward to create a thin (1 um to 10 um depending on PR viscosity and spin RPM), uniform and conformal coating over the wafer
Data Source
AI summary
Improved microchannel structures are provided using monolithic structures having deep features (≥150 um) and two or more different feature heights above the substrate. Exemplary channel structures that are enabled by this approach include step-tapered V-groove channels, channels having various kinds of lithographically define roughness, and channels having an arbitrarily defined depth along their length.