Hierarchical Microcode Storage for Multi-Core Processor Latency
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Solution Overview
Problem
Multiple-core processor implementations face challenges in microcode storage, where sharing a single instance of storage resources increases latency and design complexity, while replicating resources for each core is costly in terms of design area and power consumption.
Innovation Solution
A processor with multiple cores, each having a local microcode unit and a remote microcode unit, where microcode entries are stored locally for performance-sensitive routines and remotely for less sensitive ones, allowing efficient access and reducing resource contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single instance of microcode storage resources is shared among multiple cores, then design area and power consumption are reduced, but latency increases and performance degrades
Solution Approach 1:
The microcode storage system is segmented into local microcode units within each core and a remote shared microcode unit. Each core has its own local storage for frequently accessed microcode entries, while less frequently accessed entries are stored remotely. This segmentation allows cores to access critical microcode locally without contention, reducing latency while maintaining shared storage for other entries.
Solution Approach 2:
Different parts of the microcode storage system have different characteristics: local microcode units provide fast, low-latency access for each core, while the remote microcode unit provides centralized storage. The system assigns different access priorities and storage locations based on the specific needs of each core and microcode entry, optimizing both speed and resource utilization.
2Loss of time
If microcode storage resources are replicated for each core, then latency is reduced and performance is improved, but design area and power consumption increase
Solution Approach 1:
Instead of full replication, the system segments microcode storage into local and remote portions. Each core gets local storage for only the most critical and frequently accessed microcode entries, while other entries are shared remotely. This partial replication approach reduces the total area required compared to full replication while maintaining low latency for time-critical operations.
Solution Approach 2:
The system implements partial replication by providing local microcode storage only for the most frequently accessed entries rather than replicating the entire microcode set locally at each core. This partial action achieves the latency benefits of local storage for critical paths while avoiding the excessive area cost of complete replication.
3Device complexity
If a single instance of microcode storage is shared among multiple cores, then design complexity is reduced, but resource contention increases
Solution Approach 1:
The storage system is divided into multiple local microcode units (one per core) and a remote shared unit. This segmentation eliminates resource contention for locally stored microcode entries since each core accesses its own local unit independently. The remote unit handles only the shared entries, significantly reducing contention compared to a fully shared system while maintaining simpler design than full replication.
4Object-generated harmful factors
If microcode storage is replicated for each core, then resource contention is reduced, but power consumption increases
Solution Approach 1:
The segmented architecture with local and remote microcode units reduces power consumption compared to full replication because not all microcode entries are duplicated across all cores. The local units store only essential entries, reducing the total active storage capacity required while still eliminating contention for critical entries. The remote unit remains in a lower-power state for less frequently accessed data.
Data Source
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AI summary
A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.