Hierarchical Modulation Vector Processing for Memory Efficiency
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Solution Overview
Problem
Existing wireless communication systems face challenges in efficiently mapping information bits to higher order modulation symbol streams due to increasing memory requirements and processing overhead, particularly with higher-order modulations like 64-QAM, which limits their capacity and sensitivity to noise and interference.
Innovation Solution
A constellation mapping system using a vector processor and a fixed 16 QAM mapper with a quadrant selector to generate higher order symbols, reducing the need for multiple mapping tables and improving memory efficiency by performing hierarchical modulation with vector combination operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional lookup table approaches are used for constellation mapping in higher-order modulations (64-QAM, 256-QAM), then mapping accuracy is maintained, but memory requirements and processing overhead increase significantly
Solution Approach 1:
The patent segments the higher-order modulation constellation mapping process into multiple components: a base modulation mapper (e.g., 16-QAM) and separate quadrant selection logic. Instead of using a single large lookup table for 64-QAM or 256-QAM, the system divides the mapping into smaller manageable parts, where the base mapper handles the core symbol generation and quadrant selectors handle the additional bit mapping. This segmentation reduces memory requirements while maintaining mapping accuracy.
Solution Approach 2:
The patent implements a nested structure where higher-order modulation mapping is achieved by nesting multiple lower-order mappers and quadrant selectors. The base mapper generates fundamental symbols, and quadrant selectors nest additional mapping layers on top, effectively creating a hierarchical mapping structure. This nested approach allows the system to achieve higher-order modulation capabilities using repeated instances of simpler mapping components rather than requiring a single large lookup table.
2Productivity
If higher-order modulations (64-QAM, 256-QAM) are used to increase system throughput, then data rate increases, but sensitivity to noise and interference worsens and processing overhead increases
Solution Approach 1:
The patent segments the modulation process into a robust base mapper and additional quadrant selection stages. The base mapper (e.g., 16-QAM) uses constellation points that are more resilient to noise, while the quadrant selectors add higher-order information bits by selecting among predefined quadrants. This segmentation allows the system to achieve high data rates through multiple bits per symbol while maintaining better noise immunity in the fundamental mapping stage.
3Productivity
If higher-order modulations are used to increase system throughput, then data rate increases, but processing overhead and complexity increase
Solution Approach 1:
The patent segments the complex higher-order mapping function into simpler, reusable components: a base mapper and multiple quadrant selectors. Each quadrant selector handles a specific subset of bits and can be implemented as a simple lookup table or logic circuit. This segmentation reduces processing overhead compared to implementing a single large mapping function, as each component is computationally simpler and can be processed independently and in parallel.
Solution Approach 2:
The patent creates a universal base mapper that can serve multiple higher-order modulation schemes (64-QAM, 256-QAM, etc.) by combining it with different numbers and configurations of quadrant selectors. This multi-functional approach allows the same fundamental mapping component to support various modulation orders, reducing the need for separate processing pipelines for each modulation scheme and thereby reducing overall system complexity and processing overhead.
Data Source
AI summary
A constellation mapping method, system, and apparatus are provided for mapping a received bit stream of data to a higher order symbol vector by processing a first set of selected bits from the received bit stream with a quadrant selector to identify a first quadrant offset vector corresponding a higher order quadrant in which an intended symbol is to be mapped, processing a second set of selected bits from the received bit stream with a 16-QAM mapper to identify a 16-QAM symbol vector, transforming the 16-QAM symbol vector into a transformed 16 QAM symbol vector based on the identified higher order quadrant, and combining the transformed 16-QAM symbol vector with the first quadrant offset vector to map the bit stream of data to a higher order symbol vector.