Hierarchical Multi-Level Scheduler for Virtual Engine Lock Contention
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Solution Overview
Problem
In multi-core processor environments, increasing CPU cores lead to scheduling complexity and contention issues due to shared memory access, which can negate performance improvements by causing threads to preempt locks, preventing other threads from accessing memory spaces.
Innovation Solution
A distributed hierarchical scheduler with a primary scheduler assigning thread groups to cores and secondary schedulers managing individual thread execution, providing lock status indications to the primary scheduler to mitigate preemption and optimize resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of CPU cores is increased to enhance performance, then aggregate performance capability is improved, but scheduling complexity and lock contention increase
Solution Approach 1:
The scheduler is divided into multiple independent secondary schedulers, each associated with a specific CPU core. Each secondary scheduler manages thread scheduling for its respective core independently, reducing the global scheduling complexity that would otherwise require coordinating all cores through a single centralized scheduler.
Solution Approach 2:
The patent introduces a hierarchical scheduling structure with two levels: a primary scheduler that operates at a higher level to manage overall thread group allocation, and secondary schedulers that operate at the core level. This dimensional separation allows performance optimization at the aggregate level while simplifying execution at the individual core level.
2Adaptability or versatility
If threads are preempted to enable higher priority threads to execute, then thread scheduling flexibility is improved, but lock availability is reduced because preempted threads retain locks
Solution Approach 1:
The secondary scheduler provides feedback to the primary scheduler about the lock status of threads it is managing. This feedback mechanism allows the primary scheduler to make informed decisions about thread preemption, understanding which threads hold locks and which do not, thereby avoiding preemption of threads that would prevent other threads from acquiring needed locks.
Solution Approach 2:
The system performs preliminary assessment of lock status before executing thread preemption. By checking whether a thread holds locks before preempting it, the system prevents premature action that would leave locks unavailable, ensuring that only threads without active locks are preempted.
3Productivity
If fine-grained locking is implemented to reduce lock contention, then access efficiency is improved, but the probability of lock contention increases with more CPU cores
Solution Approach 1:
Each secondary scheduler is associated with a specific CPU core and manages locking operations locally for that core. This localizes lock management to the level of individual core execution, reducing the global contention probability that would occur if all cores shared a single lock management system.
Data Source
AI summary
A device for providing a plurality of virtual machines utilizes a multi-core processor having a plurality of cores, each with a memory cache, and a shared memory resource in communication with the cores. The device utilizes a cooperative, multi-level scheduler. The multi-level scheduler includes a primary scheduler and a plurality of secondary schedulers, each supporting a subset of the physical cores. The primary scheduler assigns a group of threads to one of the processor cores. The secondary scheduler associated with the processor core to which the group of threads was assigned schedules execution of individual ones of the threads. The secondary scheduler also provides an indication of lock status to the primary scheduler. The lock status information can be used by the primary scheduler to avoid preempting a thread that holds a lock.