Hierarchical Net Tracking Without Flattening
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Solution Overview
Problem
Traditional electronic design automation (EDA) systems require hierarchical integrated circuit designs to be flattened for efficient identification and tracking of nets, which consumes excessive memory and storage resources, especially when dealing with large numbers of geometric elements, and can be time-consuming due to the need to traverse entire hierarchies for search operations.
Innovation Solution
A method and system that allow for identifying and tracking nets in hierarchical designs without flattening, by unfolding only specific instances within the geometric bounds of identified nets, using virtual terminal structures to derive connections at other hierarchical levels, and employing shape abstraction data structures like shape trees and shadow trees to track boundaries and references.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hierarchical integrated circuit designs are flattened for efficient identification and tracking of nets, then connectivity extraction efficiency is improved, but memory and storage resource consumption increases excessively
Solution Approach 1:
The patent segments the hierarchical design data structure into multiple levels (e.g., top-level design, block-level designs, cell-level designs) and processes only the necessary segments for connectivity extraction. Instead of flattening the entire hierarchy, the system identifies and extracts connectivity information from specific segments relevant to the query, thereby reducing memory and storage resource consumption while maintaining extraction efficiency.
Solution Approach 2:
The patent extracts only the necessary connectivity information from the hierarchical design without requiring full flattening. By taking out and processing only the relevant net data and geometric elements needed for connectivity extraction, the system avoids the excessive resource consumption associated with flattening the entire design hierarchy while still achieving efficient connectivity identification.
2Measurement precision
If hierarchical integrated circuit designs are flattened for net identification, then connectivity tracking accuracy is improved, but processing time increases due to traversing entire hierarchies
Solution Approach 1:
The patent performs preliminary actions by pre-processing and indexing connectivity-relevant data at different hierarchical levels before actual connectivity extraction. This includes pre-identifying net names, creating lookup tables, and organizing geometric element references in advance, so that during connectivity extraction, the system can quickly access necessary information without traversing entire hierarchies, thus reducing processing time while maintaining accuracy.
Solution Approach 2:
The patent introduces intermediary data structures and indexing mechanisms that mediate between the hierarchical design representation and connectivity extraction operations. These intermediaries (such as netlists, lookup tables, and reference indexes) enable direct access to connectivity information without requiring full hierarchy traversal, thereby reducing processing time while preserving connectivity tracking accuracy.
3Reliability
If full flattening is performed on hierarchical designs with large numbers of geometric elements, then complete connectivity information is obtained, but system performance deteriorates due to excessive resource usage
Solution Approach 1:
The patent applies local quality by processing different portions of the hierarchical design with different levels of detail and processing intensity. For regions or nets that require complete connectivity information, full extraction is performed, while for other regions, simplified or approximate extraction is sufficient. This localized approach ensures connectivity information completeness where needed while maintaining system performance by avoiding unnecessary full flattening across the entire design.
Solution Approach 2:
The patent employs partial action by performing connectivity extraction on only the necessary portions of the hierarchical design rather than the entire structure. By identifying and processing only the relevant blocks, cells, and nets required for the specific connectivity extraction task, the system obtains complete connectivity information for those specific elements while avoiding the excessive resource usage that would result from flattening and processing the entire design hierarchy.
Data Source
AI summary
A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.