Hierarchical NoC Flow Mapping for Redundant Route Elimination
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Solution Overview
Problem
Existing methods for mapping traffic flows in Network-on-Chip (NoC) ignore the hierarchical structure of sub-NoC designs, leading to redundant mappings and increased resource configuration, which increases cost and time in hardware simulation and verification.
Innovation Solution
A method and system that utilize a hierarchical topology to identify hierarchically distinct flows across multiple instances of sub-NoC designs, determining a unified route and Virtual Channel (VC) for each flow, and projecting these back to each instance, reducing redundancy in mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hierarchical mapping is not used, then routing paths can be determined for each flow instance independently, but redundant mappings are created across multiple sub-NoC instances, increasing resource configuration and verification complexity
Solution Approach 1:
The patent merges identical routing paths across multiple sub-NoC instances by identifying hierarchically distinct flows at the parent NoC level. Instead of determining routing paths independently for each flow instance in every sub-NoC, the system combines identical paths into a single unified routing determination, which is then applied across all instances. This eliminates redundant mapping operations and reduces verification complexity while maintaining mapping accuracy.
Solution Approach 2:
The patent creates universal routing paths that can be applied across multiple sub-NoC instances. By identifying flows that are identical across instances and determining a single routing path at the parent NoC level, the system creates a universal solution that serves multiple functions simultaneously. This unified routing path can be instantiated across all relevant sub-NoC instances, reducing the overall complexity of the mapping and verification process.
2Productivity
If hierarchical mapping is not used, then each flow instance can be mapped independently, but the number of ports and buffers required increases due to redundant configurations
Solution Approach 1:
The patent merges identical routing paths across multiple sub-NoC instances by identifying hierarchically distinct flows at the parent NoC level. Instead of determining routing paths independently for each flow instance in every sub-NoC, the system combines identical paths into a single unified routing determination, which is then applied across all instances. This eliminates redundant mapping operations and reduces verification complexity while maintaining mapping accuracy.
Solution Approach 2:
The patent creates universal routing paths that can be applied across multiple sub-NoC instances. By identifying flows that are identical across instances and determining a single routing path at the parent NoC level, the system creates a universal solution that serves multiple functions simultaneously. This unified routing path can be instantiated across all relevant sub-NoC instances, reducing the overall complexity of the mapping and verification process.
Data Source
AI summary
Aspects of the present disclosure are directed to a method and a system for mapping flows of a Network-on-Chip (NoC). The method includes identifying hierarchically distinct flows across a plurality of instances of a sub-NoC, determining a unified route and Virtual Channel (VC) for each of the hierarchically distinct flows, and projecting the unified route and VC back to flow instances in each of the plurality of instances of the sub-NoC. By determining the unified route and VC for hierarchically distinct flows corresponding to flow instances of different instances of a sub-NoC, the method minimizes redundancy of mapping determination, and of resources during elaboration of NoC components.