Hierarchical On-Chip Memory Integrating CMOS and Crossbar Arrays
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Solution Overview
Problem
The complexity and cost of computer systems increase due to the use of multiple memory types, each requiring separate communication buses, protocols, and access techniques, leading to increased size and complexity.
Innovation Solution
A hierarchical on-chip memory integrates CMOS memory circuitry and crossbar memory arrays into a single integrated circuit, accessed through a common interface, combining fast access times of volatile memory with large capacity and low cost of non-volatile memory, using memristive crosspoint devices for programmable switching and data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory types are used to achieve high data density and low cost, then storage capacity increases, but device complexity and interface requirements increase
Solution Approach 1:
The patent combines volatile CMOS memory and non-volatile crossbar memory into a single integrated circuit structure, allowing both memory types to coexist and be accessed through a unified interface. This merging eliminates the need for separate communication buses and protocols for different memory types, reducing system complexity while maintaining high storage capacity through the hybrid architecture.
Solution Approach 2:
The integrated circuit is designed with universal access capabilities that can interface with both CMOS and crossbar memory technologies through a common interface. The system can adaptively access different memory types based on data requirements, providing multi-functional access pathways that reduce the need for specialized interfaces for each memory type.
2Speed
If separate communication buses are used for each memory type, then memory access is optimized, but chip count and system size increase
Solution Approach 1:
The patent merges multiple memory types into a single integrated circuit chip, eliminating the need for multiple separate chips and their associated communication buses. The unified structure allows different memory technologies to be accessed through integrated pathways within the same chip, reducing overall system size and chip count while maintaining optimized access speeds through dedicated memory controllers.
3Productivity
If different memory technologies are integrated, then data storage efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The integrated circuit is segmented into distinct functional regions, with separate CMOS memory arrays and crossbar memory arrays, each optimized for their specific functions. This segmentation allows for specialized manufacturing processes for each memory type while maintaining overall integration, making the manufacturing process more manageable despite the complexity of combining different technologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration simplifies the interface, reduces chip count, lowers costs, and minimizes size, while maintaining high data density and extending the life of non-volatile memory by optimizing data placement based on access frequency.
Implementation Method 1
using memristive crosspoint devices for programmable switching and data storage
Data Source
AI summary
A hierarchical on-chip memory (400) includes an area distributed CMOS layer (310) comprising input/output functionality and volatile memory and via array (325, 330), the area distributed CMOS layer (310) configured to selectively address the via array (325, 330). A crossbar memory (305) overlies the area distributed CMOS layer (310) and includes programmable crosspoint devices (315) which are uniquely accessed through the via array (325, 330). A method for utilizing hierarchical on-chip memory (400) includes storing frequently rewritten data in a volatile memory and storing data which is not frequently rewritten in a non-volatile memory (305), where the volatile memory is contained within an area distributed CMOS layer (310) and the non-volatile memory (305) is formed over and accessed through the area distributed CMOS layer (310).