Hierarchical Ordering Point Structure for Microprocessor Memory Coherency
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Solution Overview
Problem
In multi-core processor systems, the existing ordering architecture is inefficient when handling low-powered processing elements like I/O devices, leading to underutilization and adverse effects on system performance and response times due to the massive overhead required for high-bandwidth processing.
Innovation Solution
Implementing a hierarchical ordering point structure with a primary ordering point (POP) and auxiliary ordering points (AOPs) to manage memory operations, where the POP handles high-bandwidth tasks and AOPs handle lower-bandwidth tasks from I/O devices, optimizing resource usage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single primary ordering point (POP) is used to handle all memory operations, then high-bandwidth processing elements can maintain performance, but low-powered processing elements experience excessive overhead and reduced efficiency
Solution Approach 1:
The ordering point functionality is segmented into multiple independent units: a primary ordering point (POP) for high-bandwidth processing elements and multiple auxiliary ordering points (AOPs) for low-powered processing elements. Each ordering point handles memory operations for specific processing elements, dividing the monolithic ordering function into specialized segments that reduce overhead for each type of processing element.
Solution Approach 2:
The system dynamically switches between POP and AOP based on the active processing elements. When low-powered processing elements are active, the system uses AOPs to handle their memory operations with reduced overhead. When high-bandwidth processing elements become active, the system transitions to using POP, ensuring optimal performance for different operational scenarios.
2Reliability
If the primary ordering point (POP) is always active to ensure coherency, then system coherency is maintained, but power consumption increases during low-powered operations
Solution Approach 1:
Auxiliary ordering points (AOPs) act as intermediaries between low-powered processing elements and the primary ordering point (POP). AOPs handle memory operation ordering and coherency maintenance for low-powered elements locally, eliminating the need for POP to remain active during such operations. This intermediary layer maintains coherency reliability while reducing power consumption by keeping POP in a low-power state.
Solution Approach 2:
The system dynamically activates or deactivates the POP based on the operational state of processing elements. When only low-powered elements are active, POP is deactivated and AOPs handle coherency maintenance. When high-bandwidth elements become active, POP is activated to ensure proper coherency. This dynamic state transition maintains reliability while optimizing power consumption.
3Use of energy by moving object
If auxiliary ordering points (AOPs) are used for low-powered processing elements, then power consumption is reduced, but system responsiveness may be affected during transitions between POP and AOP
Solution Approach 1:
The system performs preliminary actions to prepare for transitions between POP and AOP modes. Before switching from POP to AOP, the system pre-configures the AOP with necessary ordering information and state data. Before switching back from AOP to POP, the system pre-synchronizes state information. This preliminary preparation minimizes transition overhead and maintains system responsiveness during mode switches.
Solution Approach 2:
The hierarchical ordering structure ensures continuous memory operation handling without interruption during transitions. While transitions between POP and AOP occur, the hierarchical design allows overlapping operations and state preservation, ensuring that memory ordering functionality continues without gaps. This continuity maintains system responsiveness by preventing idle periods during mode transitions.
Data Source
AI summary
Embodiment of this disclosure provides a hierarchical structure of ordering points. In some embodiments, the hierarchical structure includes a single primary ordering point (POP) and at least one (or more) auxiliary order point (AOP) of a processing device. In one implementation, the processing device includes one or more cores; and a coherency circuit, operatively coupled to the cores. The processing device is to receive a plurality of memory access requests to be ordered by a first ordering point of the processing device. The processing device determines whether to stop the first ordering point based on a system event. Responsive to determining that the first ordering point is stopped, a second ordering point of the processing device is identified. Thereupon, a memory access request of the plurality of memory access requests is provided to the second ordering point.