Hierarchical Output for Electronic Design Verification
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Solution Overview
Problem
Conventional approaches for verifying electronic circuit designs are limited by their flat design structure, which is ill-suited for parallelization and multi-threaded computation, and struggles with complex hierarchical control flows and state transitions, leading to inefficiencies in processing Boolean operations and dummy fill insertion.
Innovation Solution
The method involves creating a hierarchical output for Boolean operations using master output layers, global scratch layers, and inverse transforms, along with clipping and tessellation processes, to enable efficient processing and reduce duplication in electronic circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a flat design structure is used for verifying electronic circuit designs, then the verification process can be performed with conventional approaches, but the processing efficiency is limited and parallelization is difficult to implement
Solution Approach 1:
The patent divides the electronic circuit design into hierarchical levels (e.g., top-level module, sub-modules, individual cells) and processes each level separately. The verification system segments the design data into different hierarchical layers, allowing parallel processing at each level while maintaining the overall design integrity. This segmentation enables multi-threaded computation by assigning different hierarchical levels to different processing threads.
Solution Approach 2:
The patent introduces a hierarchical dimension to the traditional flat design structure. Instead of processing the design as a single flat layer, the system adds a vertical hierarchical dimension with multiple levels of abstraction. This dimensional change allows the verification process to operate simultaneously at different hierarchical levels, enabling parallelization and significantly improving processing efficiency.
2Adaptability or versatility
If conventional flat design approaches are used, then implementation is simpler, but handling complex hierarchical control flows and state transitions becomes difficult
Solution Approach 1:
The patent implements a dynamic hierarchical processing system that can adaptively navigate through different levels of the design hierarchy based on the verification requirements. The system dynamically transitions between hierarchical levels and control states, allowing flexible handling of complex control flows and state transitions while maintaining manageable processing complexity through structured hierarchical organization.
3Productivity
If Boolean operations are performed on flat design data, then the operations are straightforward to implement, but duplication occurs and processing becomes inefficient
Solution Approach 1:
The patent performs preliminary processing of design data at each hierarchical level before conducting Boolean operations. By pre-organizing and pre-processing the hierarchical data structures, the system eliminates the need for redundant data duplication during Boolean operations. The preliminary action of structuring data hierarchically enables efficient processing without repetition, improving productivity while preventing data loss through duplication.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification task in some embodiments. The methods or the systems may further determine or identify an inverse transform and apply the inverse transform to a shape before adding the shape to the hierarchical output. In some embodiments, there exists no duplication among the shapes in the hierarchical output.