Hierarchical Output Queueing for Broadband Gateway CPU Efficiency
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Solution Overview
Problem
Software implementations of hierarchical queuing models in broadband network gateways face efficiency and performance issues due to the need to manage tens of thousands of queues and rate shapers, leading to excessive CPU processing and memory access, as well as wasting CPU cycles in determining packet availability and rate shaper constraints.
Innovation Solution
The implementation of a method where packets are scheduled into queues with specific scheduled times based on Class of Service (CoS), using QBlocks with distinct availability times, allowing for efficient dequeuing and transmission without unnecessary delay, and employing rate shapers to determine the optimal enqueue time, reducing the number of queues to be scanned and minimizing CPU cycles wasted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hierarchical queuing model with tens of thousands of queues is implemented in software, then comprehensive QoS management is achieved, but CPU processing overhead and memory access time increase excessively
Solution Approach 1:
The patent segments the hierarchical queuing model into distinct functional components: rate shaper instances are separated from individual queues, and QBlocks are introduced as time-scheduled packet containers. This segmentation allows the system to manage tens of thousands of queues without proportionally increasing CPU overhead, as the rate shaper logic operates independently of queue scanning operations.
Solution Approach 2:
The patent introduces a time dimension through QBlocks with scheduled availability times. Instead of managing queues purely in terms of packet flow hierarchy, the system adds temporal scheduling as another dimension. This allows packets to be organized into time-sliced blocks that can be efficiently dequeued at predetermined intervals, reducing the need for continuous queue scanning and improving CPU efficiency.
2Manufacturing precision
If multiple rate shapers are applied to determine packet transmission timing, then accurate traffic shaping is achieved, but the number of CPU cycles required to determine optimal enqueue time increases
Solution Approach 1:
The patent applies rate shaper logic in advance to determine the future transmission time of packets before they are enqueued. By calculating the optimal enqueue time upfront based on rate shaper constraints and QBlock availability, the system avoids repeated CPU cycles during packet transmission. The rate shaper pre-computes timing information that guides subsequent enqueue operations, reducing real-time processing overhead.
3Reliability
If tens of thousands of queues are scanned to determine packet availability, then complete queue coverage is ensured, but memory access time and processing delay increase
Solution Approach 1:
The patent implements periodic queue scanning based on QBlock scheduled times rather than continuous scanning of all queues. The system scans queues at predetermined intervals corresponding to QBlock availability times, which ensures that all queues are covered periodically while minimizing the time spent on queue scanning operations. This periodic approach maintains reliability by ensuring no queue is permanently missed, while significantly reducing average scanning delay.
Data Source
AI summary
An improved method of hierarchical output queueing of packets for a network scheduler of a network gateway that determines delays needed to conform to applicable rate shaping, and enqueues the packets based on the delay. Queues are associated with different classes of service (CoS), and within each class, each queue has a different scheduled time upon which it becomes available for dequeuing. A single set of CoS queues can support a large number of devices, improving the efficiency of software-based queuing by reducing the number of queues and simplifying queue polling.