Hierarchical Parallel Partition Networks for IC Interconnects
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Solution Overview
Problem
Current integrated circuit devices with multiple processors and memories face inefficiencies in energy usage and communication latency due to the lack of optimized network architectures for interconnecting processors and memories.
Innovation Solution
A hierarchical and parallel partition network architecture is introduced, featuring unit-level and unit-to-unit switches that reduce energy expenditure by eliminating buffers at switch levels and utilizing parallel partition networks to distribute packet traffic, thereby improving energy efficiency and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional network architectures with buffers are used to interconnect processors and memories, then data transmission reliability is improved, but energy consumption increases and communication latency worsens
Solution Approach 1:
The patent removes buffers from the network switches, extracting the buffering function entirely from the network infrastructure. Data is transmitted directly from source to destination without intermediate buffering, thereby eliminating the energy consumption and latency associated with buffer operations while maintaining transmission reliability through direct point-to-point or point-to-multipoint connections.
Solution Approach 2:
The network is segmented into multiple parallel partition networks, each handling specific traffic flows. This segmentation allows data to be routed through dedicated paths without requiring centralized buffering, reducing energy consumption while maintaining reliability through redundant parallel paths.
2Productivity
If more processors and memories are added to increase computing power, then processing capability is improved, but network complexity and communication latency worsen
Solution Approach 1:
The network is divided into multiple parallel partition networks, each handling specific traffic flows between processors and memories. This segmentation scales efficiently as more processors and memories are added, as each partition can be independently extended without increasing overall network complexity. The parallel structure allows linear scaling of processing capability without quadratic growth in network complexity.
Solution Approach 2:
The patent introduces a parallel dimension to the network architecture by creating multiple partition networks that operate simultaneously. This adds a new dimension to data transmission, allowing multiple data flows to proceed in parallel rather than sequentially, thereby scaling processing capability without proportionally increasing network complexity.
3Reliability
If buffers are implemented in network switches to handle packet traffic, then data transmission reliability is improved, but communication latency increases
Solution Approach 1:
The buffering function is completely removed from network switches. Data packets are transmitted directly through the network without being queued or buffered at intermediate nodes, thereby eliminating buffer-induced latency while maintaining transmission reliability through direct connections and error detection/correction mechanisms.
Solution Approach 2:
Data transmission skips the buffering stage entirely, rushing directly from source to destination. This eliminates the time spent queuing and waiting in buffers, significantly reducing communication latency while maintaining reliability through alternative error handling mechanisms.
4Adaptability or versatility
If hierarchical network structures are used to connect processors, then scalability is improved, but energy consumption and communication latency worsen
Solution Approach 1:
The hierarchical network is segmented into parallel partition networks at each level. This segmentation allows scalability to be achieved through parallel expansion rather than deep hierarchical nesting, reducing the number of hierarchical levels data must traverse and thereby reducing energy consumption and latency while maintaining scalability.
Solution Approach 2:
The patent transforms the vertical hierarchical structure into a combination of parallel horizontal partitions and hierarchical levels. This dimensional change allows scalability to be achieved by adding parallel partitions rather than increasing hierarchical depth, thereby reducing the energy and latency costs associated with deep hierarchical traversal.
Data Source
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AI summary
In accordance with the present description, provided are hierarchical and parallel partition networks which include a plurality of parallel partition packet networks for interconnecting components on one or more integrated circuit dies. In one embodiment, each parallel partition packet network is independent of the other parallel partition packet networks and has a unit level switch at a unit hierarchical level. In another aspect, each parallel partition packet network has a unit-to-unit level switch at a unit-to-unit hierarchical level. Other aspects are described herein.