Hierarchical PCB Pin Assignment via Logical Grouping
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Solution Overview
Problem
The process of PCB layout is prone to errors due to manual handling of signal names and pin assignments, which can lead to incorrect connections between package and die or connectors, and is cumbersome when dealing with custom packages and complex designs, especially when interfacing with different EDA tools.
Innovation Solution
A PCB design flow that begins with block-level diagrams, allowing interface objects to be defined with grouping and sub-grouping, enabling logical assignments to be exported to physical layout tools without initial pin assignments, and allowing manipulation of signal groups for efficient assignment and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual pin-by-pin layout and signal assignment is used, then detailed control over connections is achieved, but error rate increases and productivity decreases
Solution Approach 1:
The patent segments the pin assignment process into two distinct phases: logical netlist creation at the block level, and physical pin assignment at the package level. This segmentation allows different teams to work at appropriate abstraction levels simultaneously, reducing errors while maintaining productivity. The logical netlist captures connectivity without requiring detailed pin knowledge, while the physical assignment phase handles the detailed pin-by-pin mapping.
Solution Approach 2:
The patent introduces an intermediary logical netlist that sits between the block-level design and the physical pin assignment. This intermediary representation captures the essential connectivity information without requiring detailed pin knowledge, serving as a bridge that allows logical design to proceed independently of physical constraints while ensuring accurate connection mapping later.
2Adaptability or versatility
If flat netlist with individual signal names is used, then tool compatibility is achieved, but complexity of managing large numbers of signals increases
Solution Approach 1:
The patent segments signals into hierarchical groups (blocks, interfaces, nets) that can be managed at appropriate levels of abstraction. Instead of treating all signals as individual flat entities, the system organizes them into nested groups that reflect the physical and logical structure of the design, making management of large signal sets tractable while maintaining tool compatibility through standardized netlist formats.
Solution Approach 2:
The patent adds a hierarchical dimension to the traditionally flat netlist structure. By organizing signals into multiple levels of grouping (blocks containing interfaces containing nets containing signals), the system transforms the one-dimensional flat list into a multi-dimensional hierarchical structure, enabling more efficient management and manipulation of large signal sets.
3Adaptability or versatility
If custom packages with non-standard pin arrangements are used, then design flexibility is improved, but difficulty of verifying connections increases
Solution Approach 1:
The patent performs preliminary logical netlist creation that captures all connection requirements before physical pin assignment to custom packages. By establishing the complete logical connectivity model in advance, the system enables automated verification of connections regardless of the final physical pin arrangement, making it easier to detect and correct errors even with highly customized packages.
Data Source
AI summary
An interface object library tool for manipulating interface objects for a printed circuit board (PCB) tool is disclosed. The interface object library tool includes a hierarchical interface display module, an input module, and a store. The hierarchical interface display module is configured to display an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines. The plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects. The input module is configured to: accept association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments; and accept association between the plurality of interface objects and a plurality of groups. The store is configured to retain the plurality of interface objects; the plurality of groups; the plurality of signal, power and ground lines; and associations between these three.