Hierarchical PLL Clocking With Low-Frequency Bypass
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Solution Overview
Problem
High power consumption and increased circuit area in clocking circuitry due to multiple levels of feedback-controlled oscillators, particularly in hierarchical configurations, which is exacerbated by the need to reduce clock signal jitter as clock speed increases.
Innovation Solution
A hierarchical arrangement of feedback-controlled oscillators where a first-level oscillator provides reference signals to second-level oscillators at higher frequencies, but bypasses them at lower frequencies to directly supply clock signals to sequential circuitry, reducing switching power consumption and circuit area by clock-gating slave PLLs in lower frequency modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple levels of feedback-controlled oscillators are implemented to provide clock signals with low jitter characteristics, then jitter is reduced, but power consumption increases
Solution Approach 1:
The system dynamically switches between two operational modes: a first mode where multiple levels of feedback-controlled oscillators are engaged to provide low jitter clock signals at higher frequencies, and a second mode where these oscillators are bypassed to reduce power consumption at lower frequencies. This dynamic adaptation resolves the contradiction by adjusting the oscillator configuration based on real-time frequency requirements.
Solution Approach 2:
The invention changes the operational parameters of the clocking system by introducing a mode selection mechanism that adjusts the number of active feedback-controlled oscillator levels based on the desired output frequency. At higher frequencies, more oscillator levels are activated to ensure low jitter, while at lower frequencies, fewer levels are activated to minimize power consumption, thus resolving the trade-off between jitter performance and power usage.
2Reliability
If multiple levels of feedback-controlled oscillators are implemented in hierarchical configuration, then clock signal jitter is reduced, but circuit area increases
Solution Approach 1:
The system dynamically configures the circuit topology by enabling or disabling specific oscillator levels based on operational mode. In the first mode, the full hierarchical chain of feedback-controlled oscillators is activated to achieve minimal jitter, utilizing the complete circuit area. In the second mode, bypass paths are activated to skip certain oscillator levels, effectively removing them from the signal path and reducing the active circuit area, thus resolving the contradiction between jitter performance and area utilization.
Solution Approach 2:
The invention changes the effective circuit area by introducing mode-selective bypass paths that alter the signal flow configuration. When operating in the second mode at lower frequencies, the bypass paths are activated, causing the clock signal to skip through intermediate feedback-controlled oscillator stages, thereby reducing the number of active circuit elements and the overall area occupied by the clocking system while maintaining acceptable performance.
3Use of energy by moving object
If second-level feedback-controlled oscillators are bypassed at lower frequencies, then power consumption is reduced, but jitter increases
Solution Approach 1:
The invention changes the operational parameters by introducing a frequency-threshold-based mode selection mechanism. When the desired output frequency exceeds a predetermined threshold, the system activates the first mode with full feedback-controlled oscillator engagement to ensure low jitter. When the frequency is below the threshold, the system switches to the second mode, bypassing certain oscillator levels to reduce power consumption. This parameter-based approach resolves the contradiction by accepting higher jitter only when frequency requirements make it acceptable.
Solution Approach 2:
The system dynamically adjusts its operational configuration based on real-time frequency requirements. The mode selection logic continuously monitors the desired clock frequency and switches between the low-power bypass mode and the low-jitter full-oscillator mode accordingly. This dynamic adaptation allows the system to optimize the trade-off between power consumption and jitter performance based on the specific operational context, resolving the contradiction by making jitter acceptable only when frequency demands permit.
Data Source
AI summary
Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).