Hierarchical Power State Table Reduction for Circuit Verification
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Solution Overview
Problem
The complexity of Power State Tables (PSTs) in circuit design increases exponentially with the number of logic gates, leading to significant time and computing resource requirements for evaluation, often taking days to complete a single evaluation.
Innovation Solution
A hierarchical verification model is applied to identify and remove Non-Peripheral Supplies (NPS) from Power State Tables, merging PSTs while applying constraints to Peripheral Supplies (PS), reducing the number of supplies and states without introducing inaccuracies, thereby simplifying the analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of logic gates in a circuit increases, then the functionality and complexity of the circuit design improve, but the time and computing resources needed to evaluate the circuit increase significantly
Solution Approach 1:
The circuit design is divided into hierarchical levels, with Power State Tables created at different levels of abstraction. This segmentation allows evaluation to proceed from higher levels (less detailed, faster) to lower levels (more detailed, slower), reducing overall evaluation time while maintaining functionality assessment.
Solution Approach 2:
The patent introduces a hierarchical dimension to the Power State Table creation process. Instead of creating a single comprehensive PST at the lowest level, multiple PSTs are created at different hierarchical levels, adding a temporal and organizational dimension to the analysis that reduces computational burden.
2Adaptability or versatility
If the number of logic gates increases, then the circuit capability improves, but the computing resources needed to evaluate the circuit increase
Solution Approach 1:
The computing workload is segmented across multiple hierarchical levels. Each level processes a subset of the total circuit complexity, distributing the computational burden and reducing the peak resource requirements needed for evaluation.
Solution Approach 2:
At higher hierarchical levels, Power State Tables are created with partial detail (omitting some lower-level specifics). This partial action provides sufficient information for high-level evaluation without requiring the full computational resources needed for complete low-level analysis at every stage.
3Measurement precision
If the number of power supplies increases, then the power modeling accuracy improves, but the complexity of modeling Power State Tables increases
Solution Approach 1:
Power supplies are managed at different hierarchical levels, with groups of power supplies analyzed at higher levels and individual power supplies analyzed at lower levels. This segmentation reduces the complexity of modeling at any single level while maintaining overall power modeling accuracy.
Solution Approach 2:
The patent adds a hierarchical level dimension to power supply modeling. Instead of managing all power supplies in a single flat structure, power supplies are organized across multiple hierarchical levels, reducing the complexity of PST modeling at each individual level.
4Reliability
If all power supplies are included in Power State Tables, then the completeness of power analysis improves, but the size and complexity of the PST increases
Solution Approach 1:
The set of all power supplies is segmented across multiple hierarchical levels. Each PST at a given level includes only the power supplies relevant to that level's scope, reducing individual PST size while maintaining overall analysis completeness through the hierarchical structure.
Solution Approach 2:
The patent introduces a hierarchical level dimension to organize power supplies in PSTs. This allows the same power supply to be represented at multiple levels with different levels of detail, reducing redundancy and overall PST complexity while maintaining complete power analysis coverage.
Data Source
AI summary
State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.