Hierarchical Proof for Formal Verification Path Sensitization

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Solution Overview

Problem

In electronic design verification, path sensitization properties often struggle to converge due to the complexity of path sensitization technology, leading to scalability issues and performance problems, especially in larger designs where security requirements are critical and formal verification's exhaustiveness may not scale well, causing state space explosion and making it difficult to prove 100% security.

Innovation Solution

A computer-implemented method that identifies higher-level instances along an electronic design path, analyzes inter-instance path information, and determines whether data can propagate from a source to a destination by abstracting logic and using a hierarchical proof strategy, allowing for iterative analysis and abstraction of logic, thereby simplifying the verification process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional formal verification is applied to larger designs, then security verification completeness is improved, but state space explosion and performance issues occur

Engineering Contradiction:
Improvesecurity verification completenessVSAvoidstate space complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the design hierarchy into higher-level instances and lower-level instances. The verification process is segmented into two stages: first verifying inter-instance paths at the higher level, then selectively verifying intra-instance paths at lower levels only when needed. This hierarchical segmentation reduces the overall state space that must be explored simultaneously, allowing security verification to scale to larger designs without exhaustive state space explosion.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If path sensitization properties are used for security verification, then verification thoroughness is improved, but convergence difficulty increases

Engineering Contradiction:
Improveverification thoroughnessVSAvoidconvergence difficulty
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies preliminary action by first performing inter-instance path sensitization analysis at the higher level before proceeding to intra-instance analysis. This preliminary verification of external paths establishes a foundation that guides subsequent detailed verification, allowing the system to identify and focus on only those instances that require deeper inspection, thereby improving convergence while maintaining thoroughness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a hierarchical dimension to the verification process, operating at multiple levels (higher-level instances and lower-level instances). This dimensional change allows path sensitization to be applied first at the abstract higher level, reducing the complexity of the verification problem before diving into detailed intra-instance analysis, thus improving convergence while preserving verification thoroughness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If detailed intra-instance analysis is performed on all instances, then verification accuracy is improved, but computational overhead increases

Engineering Contradiction:
Improveverification accuracyVSAvoidverification efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating the verification depth applied to different instances based on their characteristics and the results of inter-instance analysis. Rather than uniformly applying detailed intra-instance analysis to all instances, the system selectively applies detailed verification only to specific instances where it is necessary, thereby maintaining verification accuracy for critical paths while improving overall productivity by avoiding unnecessary detailed analysis of other instances.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11507492B1Applying a hierarchical proof to formal verification based path sensitization
Publication Date: 2022.11.22 CADENCE DESIGN SYST INC
  • US11507492B1 patent drawing
  • US11507492B1 patent drawing
  • US11507492B1 patent drawing

AI summary

The present disclosure relates to a method for electronic design verification. Embodiments may include identifying a plurality of higher level instances along an electronic design path from a source to a destination. Embodiments may further include analyzing inter-instance path information associated with the plurality of higher level instances included in the electronic design path from source to destination. Analyzing may include ignoring information included within the plurality of higher level instances. Embodiments may further include determining, based upon, at least in part, inter-instance path information whether data is unable to propagate from the source to the destination.