Hierarchical Reset Logic for Memory Array Area Reduction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing memory units without reset capabilities require complex and costly implementation of resettable flip-flops, leading to slower performance and increased silicon surface area, making it challenging to design resettable memories efficiently.

Innovation Solution

The implementation of a hierarchical reset approach using fewer resettable storage cells, where a finite state machine or counter indicates reset status, and reset information is propagated efficiently across memory units, reducing the number of required resettable cells and optimizing silicon area usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resettable flip-flops with complicated multiplexing and control circuitry are used to implement each storage cell, then reset functionality is achieved, but performance deteriorates and silicon surface area increases

Engineering Contradiction:
Improvereset functionalityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory into groups of storage cells, where each group is controlled by a single resettable storage cell rather than requiring each cell to be individually resettable. This segmentation allows reset functionality to be achieved at the group level, reducing overall complexity while maintaining necessary reset capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The resettable storage cell serves multiple functions: it acts as both a data storage element and a reset control signal generator for its associated group of storage cells. This multi-functionality eliminates the need for separate reset control circuitry for each storage cell, thereby improving performance while maintaining reset functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If resettable flip-flops with complicated multiplexing and control circuitry are used to implement each storage cell, then reset functionality is achieved, but silicon surface area increases

Engineering Contradiction:
Improvereset functionalityVSAvoidsilicon surface area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the memory into groups of storage cells, where each group is controlled by a single resettable storage cell rather than requiring each cell to be individually resettable. This segmentation allows reset functionality to be achieved at the group level, reducing overall complexity while maintaining necessary reset capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The resettable storage cell serves multiple functions: it acts as both a data storage element and a reset control signal generator for its associated group of storage cells. This multi-functionality eliminates the need for separate reset control circuitry for each storage cell, thereby improving performance while maintaining reset functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If hierarchical reset approach with fewer resettable storage cells is used, then silicon area is reduced, but reset information propagation complexity increases

Engineering Contradiction:
Improvesilicon surface areaVSAvoidreset information propagation
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the memory into groups of storage cells, where each group is controlled by a single resettable storage cell rather than requiring each cell to be individually resettable. This segmentation allows reset functionality to be achieved at the group level, reducing overall complexity while maintaining necessary reset capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The resettable storage cell acts as an intermediary between the reset control signal and the group of storage cells it controls. It receives the reset signal and automatically propagates the reset information to its associated storage cells, eliminating the need for complex external control circuitry while simplifying the propagation process.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If hierarchical reset approach with fewer resettable storage cells is used, then mapper software run time decreases, but design complexity increases

Engineering Contradiction:
Improvemapper software run timeVSAvoiddesign complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the memory into groups of storage cells, where each group is controlled by a single resettable storage cell rather than requiring each cell to be individually resettable. This segmentation allows reset functionality to be achieved at the group level, reducing overall complexity while maintaining necessary reset capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The resettable storage cell acts as an intermediary between the reset control signal and the group of storage cells it controls. It receives the reset signal and automatically propagates the reset information to its associated storage cells, eliminating the need for complex external control circuitry while simplifying the propagation process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8705259B2Resettable memory apparatuses and design
Publication Date: 2014.04.22 SYNOPSYS INC
  • US8705259B2 patent drawing
  • US8705259B2 patent drawing
  • US8705259B2 patent drawing

AI summary

In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a portion of the memory units in response to one of the resettable memory cells having a reset value when one of the memory units is written into.